參數(shù)資料
型號(hào): DS21552GN
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 75/137頁(yè)
文件大?。?/td> 0K
描述: IC TXRX T1 1-CHIP 5V 100-BGA
標(biāo)準(zhǔn)包裝: 1
功能: 單芯片收發(fā)器
接口: E1,HDLC,J1,T1
電路數(shù): 1
電源電壓: 4.75 V ~ 5.25 V
電流 - 電源: 75mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 100-LFBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 100-CSBGA(10x10)
包裝: 托盤(pán)
包括: DSX-1 和 CSU 線路補(bǔ)償發(fā)生器,HDLC 控制器,帶內(nèi)回路代碼發(fā)生器和檢測(cè)器
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)當(dāng)前第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)
DS21352/DS21552
42 of 137
CCR7: COMMON CONTROL REGISTER 7 (Address=0A Hex)
(MSB)
(LSB)
LIRST
RLB
RESR
TESR
LIUSI
CDIG
LIUODO
SYMBOL
POSITION
NAME AND DESCRIPTION
LIRST
CCR7.7
Line Interface Reset. Setting this bit from a zero to a one will initiate an internal reset
that affects the clock recovery state machine and jitter attenuator. Normally this bit is
only toggled on power–up. Must be cleared and set again for a subsequent reset.
RLB
CCR7.6
Remote Loopback.
0 = loopback disabled
1 = loopback enabled
RESR
CCR7.5
Receive Elastic Store Reset. Setting this bit from a zero to a one will minimize the
delay through the receive elastic store. Should be toggled after RSYSCLK has been
applied and is stable. See section 14.3 for details. Do not leave this bit set HIGH.
TESR
CCR7.4
Transmit Elastic Store Reset. Setting this bit from a zero to a one will maximize the
delay through the transmit elastic store. Transmit data is lost during the reset. Should be
toggled after TSYSCLK has been applied and is stable. See section 14.3for details. Do
not leave this bit set HIGH.
-CCR7.3
Reserved. Must be set low for proper operation.
LIUSI
CCR7.2
Line Interface Synchronization Interface Enable. This control bit determines whether
the line receiver should handle a normal T1 signal or a 1.544MHz synchronization signal.
This control has no affect on the line interface transmitter.
0 = line receiver configured to support a normal T1 signal
1 = line receiver configured to support a synchronization signal
CDIG
CCR7.1
Customer Disconnect Indication Generator. This control bit determines whether the
Line Interface will generate an unframed ...1010... pattern at TTIP and TRING instead of
the normal data pattern.
0 = generate normal data at TTIP & TRING as input via TPOSI & TNEGI
1 = generate a ...1010... pattern at TTIP and TRING
LIUODO
CCR7.0
Line Interface Open Drain Option. This control bit determines whether the TTIP and
TRING outputs will be open drain or not. The line driver outputs can be forced open
drain to allow 6Vpeak pulses to be generated or to allow the creation of a very low power
interface.
0 = allow TTIP and TRING to operate normally
1 = force the TTIP and TRING outputs to be open drain
6.6 REMOTE LOOPBACK
When CCR7.6 is set to a one, the DS21352/552 will be forced into Remote LoopBack (RLB). In this
loopback, data input via the RPOSI and RNEGI pins will be transmitted back to the TPOSO and TNEGO
pins. Data will continue to pass through the receive side framer of the DS21352/552 as it would normally
and the data from the transmit side formatter will be ignored. Please see Figure 3-1 for more details.
相關(guān)PDF資料
PDF描述
VE-B7Y-IY-B1 CONVERTER MOD DC/DC 3.3V 33W
S9S12HY32J0MLH MCU 32K FLASH AUTO 64-LQFP
VE-B6Z-IX-B1 CONVERTER MOD DC/DC 2V 30W
S9S08DN48F1MLF IC MCU 8BIT 48KB FLASH 48LQFP
MC9S08DV60ACLF IC MCU 60K FLASH 3K RAM 48-LQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS21552L 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 5V T1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流(最大值):595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21552L+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 5V T1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流(最大值):595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21552LB 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述:
DS21552LN 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 5V T1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流(最大值):595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21552LN+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 5V T1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流(最大值):595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray