參數(shù)資料
型號: DS21554LN
廠商: Maxim Integrated Products
文件頁數(shù): 52/124頁
文件大小: 0K
描述: IC TXRX E1 1-CHIP 5V 100-LQFP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
產(chǎn)品變化通告: Product Discontinuation 20/Feb/2012
標準包裝: 90
功能: 單芯片收發(fā)器
接口: E1,HDLC,J1,T1
電路數(shù): 1
電源電壓: 4.75 V ~ 5.25 V
電流 - 電源: 75mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應商設(shè)備封裝: 100-LQFP(14x14)
包裝: 托盤
包括: 遠程和 AIS 警報檢測器 / 發(fā)生器
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
33 of 124
RCR2: RECEIVE CONTROL REGISTER 2 (Address = 11 Hex)
(MSB)
(LSB)
Sa8S
Sa7S
Sa6S
Sa5S
Sa4S
RBCS
RESE
SYMBOL
POSITION
NAME AND DESCRIPTION
Sa8S
RCR2.7
Sa8 Bit Select. Set to one to have RLCLK pulse at the Sa8 bit position;
set to zero to force RLCLK low during Sa8 bit position. See Section 18.1
for timing details.
Sa7S
RCR2.6
Sa7 Bit Select. Set to one to have RLCLK pulse at the Sa7 bit position;
set to zero to force RLCLK low during Sa7 bit position. See Section 18.1
for timing details.
Sa6S
RCR2.5
Sa6 Bit Select. Set to one to have RLCLK pulse at the Sa6 bit position;
set to zero to force RLCLK low during Sa6 bit position. See Section 18.1
for timing details.
Sa5S
RCR2.4
Sa5 Bit Select. Set to one to have RLCLK pulse at the Sa5 bit position;
set to zero to force RLCLK low during Sa5 bit position. See Section 18.1
for timing details.
Sa4S
RCR2.3
Sa4 Bit Select. Set to one to have RLCLK pulse at the Sa4 bit position;
set to zero to force RLCLK low during Sa4 bit position. See Section 18.1
for timing details.
RBCS
RCR2.2
Receive-Side Backplane Clock Select.
0 = if RSYSCLK is 1.544 MHz
1 = if RSYSCLK is 2.048/4.096/8.192 MHz
RESE
RCR2.1
Receive-Side Elastic Store Enable.
0 = elastic store is bypassed
1 = elastic store is enabled
RCR2.0
Not Assigned. Should be set to zero when written.
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PDF描述
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