參數(shù)資料
型號: DS21FT42N
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PBGA300
封裝: 27 X 27 MM, BGA-300
文件頁數(shù): 47/115頁
文件大?。?/td> 534K
代理商: DS21FT42N
DS21FF42/DS21FT42
37 of 115
FRAMER LOOPBACK
When CCR1.0 is set to a one, the DS21Q42 will enter a Framer LoopBack (FLB) mode. This loopback
is useful in testing and debugging applications. In FLB, the DS21Q42 will loop data from the transmit
side back to the receive side. When FLB is enabled, the following will occur:
1. An unframed all one’s code will be transmitted at TPOS and TNEG
2. Data at RPOS and RNEG will be ignored
3. All receive side signals will take on timing synchronous with TCLK instead of RCLK
Please note that it is not acceptable to have RCLK tied to TCLK during this loopback because this will
cause an unstable condition.
CCR2: COMMON CONTROL REGISTER 2 (Address=38 Hex)
(MSB)
(LSB)
TFM
TB8ZS
TSLC96
TZSE
RFM
RB8ZS
RSLC96
RZSE
SYMBOL
POSITION
NAME AND DESCRIPTION
TFM
CCR2.7
Transmit Frame Mode Select.
0 = D4 framing mode
1 = ESF framing mode
TB8ZS
CCR2.6
Transmit B8ZS Enable.
0 = B8ZS disabled
1 = B8ZS enabled
TSLC96
CCR2.5
Transmit SLC–96 / Fs–Bit Insertion Enable. Only set this
bit to a one in D4 framing applications. Must be set to one to
source the Fs pattern. See Section 19 for details.
0 = SLC–96/Fs–bit insertion disabled
1 = SLC–96/Fs–bit insertion enabled
TZSE
CCR2.4
Transmit FDL Zero Stuffer Enable. Set this bit to zero if
using the internal HDLC/BOC controller instead of the
legacy support for the FDL. See Section 19 for details.
0 = zero stuffer disabled
1 = zero stuffer enabled
RFM
CCR2.3
Receive Frame Mode Select.
0 = D4 framing mode
1 = ESF framing mode
RB8ZS
CCR2.2
Receive B8ZS Enable.
0 = B8ZS disabled
1 = B8ZS enabled
RSLC96
CCR2.1
Receive SLC–96 Enable. Only set this bit to a one in
D4/SLC–96 framing applications. See Section 19 for details.
0 = SLC–96 disabled
1 = SLC–96 enabled
相關(guān)PDF資料
PDF描述
DS21FF42 DATACOM, FRAMER, PBGA300
DS21FF42N DATACOM, FRAMER, PBGA300
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