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| 型號： | DS21Q348N |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 44/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU T1/E1/J1 QUAD 3.3V 144BGA |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 類型： | 線路接口裝置（LIU） |
| 規(guī)程： | E1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-BBGA |
| 供應(yīng)商設(shè)備封裝： | 144-PBGA（17x17） |
| 包裝： | 管件 |
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DS21348/DS21Q348
49 of 76
7. ANALOG INTERFACE
7.1 Receiver
The DS21348 contains a digital clock recovery system. The DS21348 couples to the receive E1 or T1
twisted pair (or coaxial cable in 75 E1 applications) via a 1:1 transformer. See Table 7-3 for transformer
termination requirements. The DS21348 has the option of using internal termination resistors.
The DS21348 is designed to be fully software-selectable for E1 and T1 without the need to change any
external resistors for the receive-side. The receive-side will allow the user to configure the DS21348 for
75, 100, or 120 receive termination by setting the RT1 (CCR5.1) and RT0 (CCR5.0) bits. When
using the internal termination feature, the Rr resistors should be 60 each. See Figure 7-1 for details. If
external termination is required, RT1 and RT0 should be set to 0 and both Rr resistors in Figure 7-1 will
need to be 37.5, 50, or 60 each depending on the line impedance.
The resultant E1 or T1 clock derived from the 2.048/1.544 PLL (JACLK in Figure 1-1) is internally
multiplied by 16 via another internal PLL and fed to the clock recovery system. The clock recovery
system uses the clock from the PLL circuit to form a 16 times oversampler which is used to recover the
clock and data. This oversampling technique offers outstanding performance to meet jitter tolerance
specifications shown in Figure 7-6.
Normally, the clock that is output at the RCLK pin is the recovered clock from the E1 AMI/HDB3 or T1
AMI/B8ZS waveform presented at the RTIP and RRING inputs. When no signal is present at RTIP and
RRING, a Receive Carrier Loss (RCL) condition will occur and the RCLK will be derived from the
JACLK source. See Figure 1-1. If the jitter attenuator is placed in the receive path (as is the case in most
applications), the jitter attenuator restores the RCLK to an approximate 50% duty cycle. If the jitter
attenuator is either placed in the transmit path or is disabled, the RCLK output can exhibit slightly shorter
high cycles of the clock. This is due to the highly oversampled digital clock recovery circuitry. See the
Receive AC Timing Characteristics in Section 11 for more details.
The receive-side circuitry also contains a clock synthesizer which outputs a user configurable clock (up to
16.384MHz) synthesized to RCLK at BPCLK (pin 31). See Table 4-3 for details on output clock
frequencies at BPCLK. In hardware mode, BPCLK defaults to a 16.384MHz output.
The DS21348 has a bypass mode for the receive side clock and data. This allows the BPCLK to be
derived from RCLK after the jitter attenuator while the clock and data presented at RCLK, RPOS, and
RNEG go unaltered. This is intended for applications where the receive side jitter attenuation will be
done after the LIU. Setting RJAB (CCR6.3) to a logic 1 will enable the bypass. Be sure that the jitter
attenuator is in the receive path (CCR4.3 = 0). See Figure 1-1 for details.
The DS21348 will report the signal strength at RTIP and RRING in 2.5dB increments via RL3-RL0
located in the Receive Information Register 2. This feature is helpful when trouble shooting line
performance problems. See Table 5-2 for details.
Monitor applications in both E1 and T1 require various flat gain settings for the receive-side circuitry.
The DS21348 can be programmed to support these applications via the Monitor Mode control bits MM1
and MM0. When the monitor modes are enabled, the receiver will tolerate normal line loss up to -6dB.
See Table 4-4 for details.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS21Q348NB | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q348-W | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q352 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3/5V Quad T1/E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q352B | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3/5V Quad T1/E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q352B+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3/5V Quad T1/E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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