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參數(shù)資料
| 型號(hào)： | DS21Q55N |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Quad T1/E1/J1 Transceiver |
| 中文描述： | 四路T1/E1/J1收發(fā)器 |
| 文件頁(yè)數(shù)： | 111/237頁(yè) |
| 文件大?。?/td> | 1438K |
| 代理商： | DS21Q55N |
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DS21Q55 Quad T1/E1/J1 Transceiver
111 of 237
17.1 Receive Side
See the IOCR1 and IOCR2 registers for information about clock and I/O configurations.
If the receive-side elastic store is enabled, then the user must provide either a 1.544MHz or 2.048MHz
clock at the RSYSCLK pin. For higher rate system clock applications, see the
Interleaved PCM Bus
Operation
in Section
26
. The user has the option of either providing a frame/multiframe sync at the
RSYNC pin or having the RSYNC pin provide a pulse on frame/multiframe boundaries. If signaling
reinsertion is enabled, signaling data in TS16 is realigned to the multiframe sync input on RSYNC.
Otherwise, a multiframe sync input on RSYNC is treated as a simple frame boundary by the elastic store.
The framer always indicates frame boundaries on the network side of the elastic store by the RFSYNC
output, whether the elastic store is enabled or not. Multiframe boundaries are always indicated by the
RMSYNC output. If the elastic store is enabled, then RMSYNC outputs the multiframe boundary on the
backplane side of the elastic store.
17.1.1 T1 Mode
If the user selects to apply a 2.048MHz clock to the RSYSCLK pin, then the data output at RSER is
forced to all 1s every fourth channel and the F-bit is passed into the MSB of TS0. Hence, channels 1 (bits
1–7), 5, 9, 13, 17, 21, 25, and 29 [time slots 0 (bits 1–7), 4, 8, 12, 16, 20, 24, and 28] are forced to a 1.
Also, in 2.048MHz applications, the RCHBLK output is forced high during the same channels as the
RSER pin. This is useful in T1-to-E1 conversion applications. If the two-frame elastic buffer either fills
or empties, a controlled slip occurs. If the buffer empties, then a full frame of data is repeated at RSER,
and the SR5.0 and SR5.1 bits are set to a 1. If the buffer fills, then a full frame of data is deleted, and the
SR5.0 and SR5.2 bits are set to a 1.
17.1.2 E1 Mode
If the elastic store is enabled, then either CAS or CRC4 multiframe boundaries are indicated through the
RMSYNC output. If the user selects to apply a 1.544MHz clock to the RSYSCLK pin, then every fourth
channel of the received E1 data is deleted and an F-bit position, which is forced to 1, is inserted. Hence,
channels 1, 5, 9, 13, 17, 21, 25, and 29 (time slots 0, 4, 8, 12, 16, 20, 24, and 28) are deleted from the
received E1 data stream. Also, in 1.544MHz applications, the RCHBLK output is not active in channels
25 through 32 (i.e., RCBR4 is not active). If the two-frame elastic buffer either fills or empties, a
controlled slip occurs. If the buffer empties, then a full frame of data is repeated at RSER, and the SR5.0
and SR5.1 bits are set to a 1. If the buffer fills, then a full frame of data is deleted, and the SR5.0 and
SR5.2 bits are set to a 1.
17.2 Transmit Side
See the IOCR1 and IOCR2 registers for information about clock and I/O configurations.
The operation of the transmit elastic store is very similar to the receive side. If the transmit-side elastic
store is enabled, a 1.544MHz or 2.048MHz clock can be applied to the TSYSCLK input. For higher rate
system clock applications, see
Interleaved PCM Bus Operation
in Section
26
. Controlled slips in the
transmit elastic store are reported in the SR5.3 bit, and the direction of the slip is reported in the SR5.4
and SR5.5 bits. If hardware signaling insertion is not enabled, CCR3.7 should be set = 1.
相關(guān)PDF資料 |
PDF描述 |
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| DS21S07A | SCSI Terminator |
| DS21S07AE | Terminator |
| DS21S07AS | Terminator |
| DS21S07CE | Interface IC |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS21Q58 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:E1 Quad Transceiver |
| DS21Q58L | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q58L+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q58LN | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q58LN+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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