參數(shù)資料
型號: DS26324GNA3+
廠商: Maxim Integrated Products
文件頁數(shù): 35/120頁
文件大小: 0K
描述: IC LIU E1/T1/J1 3.3V 256-CSBGA
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 90
類型: 線路接口裝置(LIU)
驅動器/接收器數(shù): 16/16
規(guī)程: LIN
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 256-LBGA,CSBGA
供應商設備封裝: 256-CSBGA(17x17)
包裝: 托盤
DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit
21 of 120
Table 5-2. Telecommunications Specification Compliance for DS26324 Transmitters
TRANSMITTER FUNCTION
TELECOMMUNICATIONS COMPLIANCE
AMI Coding, B8ZS Substitution, DS1 Electrical Interface
ANSI T1.102
T1 Telecom Pulse Mask compliance
ANSI T1.403
T1 Telecom Pulse Mask compliance
ANSI T1.102
Transmit Electrical Characteristics for E1 Transmission
and Return Loss Compliance
ITU-T G.703
Table 5-3. Registers Related to Control of DS26324 Transmitters
REGISTER
NAME
FUNCTION
Transmit All Ones Enable
Transmit all ones enable.
Driver Fault Monitor Status
Driver fault status.
Driver Fault Monitor Interrupt Enable
Driver fault status interrupt mask.
Driver Fault Monitor Interrupt Status
Driver fault status interrupt mask.
Automatic Transmit All Ones Select
Transmit all ones enabled automatically on LOS.
Global Configuration
Global control of jitter attenuator, line coding and short
circuit protection.
Template Select Transmitter
The transmitter that the Template Select Transmitter
Register applies to.
Template Select
The TS2 to TS0 bits for selection of the templates for
transmitter and TIMPOFF and TIMPRIM bits to control
transmit impedance match.
Output Enable Configuration
These register bits can be used to enable the transmitter
outputs.
Master Clock Selection
Selects the MCLK frequency used for transmit and
receive.
Single-Rail Mode Select
This register can be used to select between single-rail
and dual-rail mode.
Line Code Selection
The individual transceiver line codes can be selected to
overwrite the global setting.
Transmit Power-Down Enable
Individual transmitters can be powered down.
Individual Jitter Attenuator Enable
Enables the jitter attenuator.
Individual Jitter Attenuator Position
Select
Selects whether jitter attenuator is in transmit or receive
path
Individual Jitter Attenuator FIFO
Depth Select
Selects depth of jitter attenuator FIFO.
Individual Jitter Attenuator FIFO
Limit Trip
Indicates jitter attenuator FIFO within 4 bits of its useful
limit.
Individual Short-Circuit Protection
Disable
This register allows the individual transmitters to have
short-circuit protection disable.
Bit Error Rate Tester Control
This register allows mapping of the internal BERTs into
an individual transmit path.
Transmit Clock Invert
Inverts TCLK input.
BPV Error Insertion
Inserts a bipolar error in the transmit path when in single-
rail mode.
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