
DS26524 Quad T1/E1/J1 Transceiver
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NAME
PIN
TYPE
FUNCTION
RCHBLK/
CLK1
E4
RCHBLK/
CLK2
B5
RCHBLK/
CLK3
L6
RCHBLK/
CLK4
T5
O
Receive Channel Block/Receive Channel Block Clock. This pin can be
configured to output either RCHBLK or RCHCLK. RCHBLK is a user-
programmable output that can be forced high or low during any of the 24 T1 or 32
E1 channels. It is synchronous with RCLK when the receive-side elastic store is
disabled. It is synchronous with RSYSCLK when the receive-side elastic store is
enabled. This pin is useful for blocking clocks to a serial UART or LAPD controller
in applications where not all channels are used such as fractional service, 384kbps
service, 768kbps, or ISDN-PRI. Also useful for locating individual channels in drop-
and-insert applications, for external per-channel loopback, and for per-channel
conditioning.
RCHCLK. RCHCLKn is a dual function pin that can output either a gapped clock or
a channel clock. In gapped clock mode, RCHCLKn is a N x 64kHz fractional clock
that is software programmable for 0 to 24 channels and the F-bit (T1) or 0 to 32
channels (E1). In channel clock mode, RCHCLKn is a 192kHz (T1) or 256kHz (E1)
clock that pulses high during the LSB of each channel. It is useful for parallel-to-
serial conversion of channel data. In either mode, RCHCLK is synchronous with
RCLKn when the receive-side elastic store is disabled or it is synchronous with
RSYSCLKn when the receive-side elastic store is enabled. The mode of
RCHCLKn is determined by the RGCLKEN bit in the RESCR register.
BPCLK
E8
O
Backplane Clock. Programmable clock output that can be set to 2.048MHz,
4.096MHz, 8.192MHz, or 16.384MHz. The reference for this clock can be RCLK
from any of the LIU, 1.544MHz, or 2.048MHz frequency derived from MCLK or an
external reference clock. This allows for the IBO clock to reference from external
source or T1J1E1 recovered clock or the MCLK oscillator.
MICROPROCESSOR INTERFACE
A12
C8
A11
A8
A10
B8
A9
F8
A8
B9
A7
A9
A6
C9
A5
D9
A4
E9
A3
F9
A2
B10
A1
A10
A0
C10
I
Address [12:0]. This bus selects a specific register in the DS26524 during
read/write access. A12 is the MSB and A0 is the LSB.
D7
T9
D6
N9
D5
M9
D4
R8
D3
T8
D2
P8
D1
L9
D0
N8
I
Data [7:0]. This 8-bit, bidirectional data bus is used for read/write access of the
DS26524 information and control registers. D7 is the MSB and D0 is the LSB.
CSB
T7
I
Chip-Select Bar. This active-low signal is used to qualify register read/write
accesses. The
RDB/DSB and WRB signals are qualified with CSB.
RDB/
DSB
M8
I
Read-Data Bar/Data-Strobe Bar. This active-low signal along with
CSB qualifies
read access to one of the DS26524 registers. The DS26524 drives the data bus
with the contents of the addressed register while
RDB and CSB are low.
WRB/
RWB
R7
I
Write-Read Bar/Read-Write Bar. This active-low signal along with
CSB qualifies
write access to one of the DS26524 registers. Data at D[7:0] is written into the
addressed register at the rising edge of
WRB while CSB is low.