參數(shù)資料
型號(hào)： DS26524DK
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 199/273頁(yè)
文件大?。?/td> 0K
描述： KIT DESIGN FOR DS26524
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1
主要目的： 電信，調(diào)幀器和線路接口裝置（LIU）
已用 IC / 零件： DS26524
已供物品： 板，子卡，線纜，CD，文檔
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DS26524 Quad T1/E1/J1 Transceiver
31 of 273
8.8
System Backplane Interface
The DS26524 provides a versatile backplane interface that can be configured to the following:
Transmit and receive two-frame elastic stores
Mapping of T1 channels into a 2.048MHz backplane
IBO mode for multiple framers to share the backplane signals
Transmit and receive channel-blocking capability
Fractional T1/E1/J1 support
Hardware-based (through the backplane interface) or processor-based signaling
Flexible backplane clock providing frequencies of 2.048MHz, 4.096MHz, 8.192MHz, 16.384MHz
Backplane clock and frame pulse (TSSYNCIOn) generator
8.8.1 Elastic Stores
The DS26524 contains dual two-frame elastic stores for each framer: one for the receive direction and one for the
transmit direction. Both elastic stores are fully independent. The transmit- and receive-side elastic stores can be
enabled/disabled independently of each other. Also, the transmit or receive elastic store can interface to either a
1.544MHz or 2.048/4.096/8.192/16.384MHz backplane without regard to the backplane rate for the other elastic
store. Since the DS26524 has a common TSYSCLK and RSYSCLK for all four ports, the backplane signals in each
direction must be synchronous for all ports on which the elastic stores are enabled. However, the transmit and
receive signals are not required to be synchronous to each other. The TIOCR and RIOCR settings should be
identical for all ports on which the elastic stores are enabled.
The elastic stores have two main purposes. First, they can be used for rate conversion. When the DS26524 is in
the T1 mode, the elastic stores can rate convert the T1 data stream to a 2.048MHz backplane. In E1 mode the
elastic store can rate convert the E1 data stream to a 1.544MHz backplane. Second, the elastic stores can be used
to absorb the differences in frequency and phase between the T1 or E1 data stream and an asynchronous (i.e., not
locked) backplane clock, which can be 1.544MHz or 2.048MHz. In this mode, the elastic stores manage the rate
difference and perform controlled slips, deleting or repeating frames of data to manage the difference between the
network and the backplane.
If the elastic store is enabled while in E1 mode, then either CAS or CRC-4 multiframe boundaries are indicated via
the RMSYNC output as controlled by the RSMS2 control bit (RIOCR.1). If the user selects to apply a 1.544MHz
clock to the RSYSCLK pin, then the Receive Blank Channel Select registers (RBCS1:RBCS4) registers determine
which channels of the received E1 data stream will be deleted. In this mode an F-bit location is inserted into the
RSER data and set to 1. Also, in 1.544MHz applications, the RCHBLK output will not be active in Channels 25 to
32 (or in other words, RCBR4 is not active). If the two-frame elastic buffer either fills or empties, a controlled slip
occurs. If the buffer empties, a full frame of data is repeated at RSER and the RLS4.5 and RLS4.6 bits are set to 1.
If the buffer fills, a full frame of data is deleted and the RLS4.5 and RLS4.7 bits are set to 1.
The elastic stores can also be used to multiplex T1 or E1 data streams into higher backplane rates. This is the
Interleave Bus Option (IBO), which is discussed in Section 8.8.2. Table 8-2 shows the registers related to the
elastic stores.
Table 8-2. Registers Related to the Elastic Store
REGISTER
FRAMER
ADDRESSES
FUNCTION
Receive I/O Configuration Register (RIOCR)
084h
Sync and clock selection for the receiver.
Receive Elastic Store Control Register
085h
Receive elastic store control.
Receive Latched Status Register 4 (RLS4)
093h
Receive elastic store empty full status.
Receive Interrupt Mask Register 4 (RIM4)
0A3h
Receive interrupt mask for elastic store.
Transmit Elastic Store Control Register
185h
Transmit elastic control such as minimum
mode.
Transmit Latched Status Register 1 (TLS1)
190h
Transmit elastic store latched status.
Transmit Interrupt Mask Register 1 (TIM1)
1A0h
Transmit elastic store interrupt mask.
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200h), where n = 2 to 4 for Framers 2 to 4.
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DS26524G 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4-Port E1/T1/J1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS26524G+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4-Port E1/T1/J1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS26524GA4 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS26524GA5 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4-Port E1/T1/J1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS26524GA5+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4-Port E1/T1/J1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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