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參數(shù)資料
| 型號(hào)： | DS26524DK |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 200/273頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | KIT DESIGN FOR DS26524 |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 電信，調(diào)幀器和線路接口裝置（LIU） |
| 已用 IC / 零件： | DS26524 |
| 已供物品： | 板，子卡，線纜，CD，文檔 |
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DS26524 Quad T1/E1/J1 Transceiver
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8.8.1.1 Elastic Stores Initialization
There are two elastic store initializations that can be used to improve performance in certain applications: elastic
store reset and elastic store align. Both of these involve the manipulation of the elastic store’s read and write
pointers and are useful primarily in synchronous applications (RSYSCLK/TSYSCLK are locked to RCLK/TCLK,
respectively). The elastic store reset is used to minimize the delay through the elastic store. The elastic store align
bit is used to “center” the read/write pointers to the extent possible.
Table 8-3. Elastic Store Delay After Initialization
INITIALIZATION
REGISTER BIT
DELAY
Receive Elastic Store Reset
N bytes < Delay < 1 Frame + N bytes
Transmit Elastic Store Reset
N bytes < Delay < 1 Frame + N bytes
Receive Elastic Store Align
1/2 Frame < Delay < 1 1/2 Frames
Transmit Elastic Store Align
1/2 Frame < Delay < 1 1/2 Frames
N = 9 for RSZS = 0; N = 2 for RSZS = 1.
8.8.1.2 Minimum Delay Mode
Elastic store minimum-delay mode can be used when the elastic store’s system clock is locked to its network clock
(i.e., RCLK locked to RSYSCLK for the receive side and TCLK locked to TSYSCLK for the transmit side).
RESCR.1 enables the receive elastic store minimum-delay mode. When enabled, the elastic stores are forced to a
maximum depth of 32 bits instead of the normal two-frame depth. This feature is useful primarily in applications that
interface to a 2.048MHz bus. Certain restrictions apply when minimum-delay mode is used. In addition to the
restriction mentioned above, RSYNC must be configured as an output when the receive elastic store is in
minimum-delay mode and TSYNC must be configured as an output when transmit minimum-delay mode is
enabled. In this mode the SYNC outputs are always in frame mode (multiframe outputs are not allowed). In a
typical application, RSYSCLK and TSYSCLK are locked to RCLK and RSYNC (frame-output mode) is connected to
TSSYNCIO (frame-input mode). The slip zone select bit (RSZS at RESCR.4) must be set to 1. All the slip
contention logic in the framer is disabled (since slips cannot occur). On power-up, after the RSYSCLK and
TSYSCLK signals have locked to their respective network clock signals, the elastic store reset bit (RESCR.2)
should be toggled from a 0 to 1 to ensure proper operation
8.8.1.3 Additional Receive Elastic Store Information
If the receive-side elastic store is enabled, the user must provide either a 1.544MHz or 2.048MHz clock at the
RSYSCLK pin. See Section 8.8.2 for higher rate system-clock applications. The user has the option of either
providing a frame/multiframe sync at the RSYNC pin or having the RSYNC pin provide a pulse on frame/multiframe
boundaries. If signaling reinsertion is enabled, the robbed-bit signaling data is realigned to the multiframe sync
input on RSYNC. Otherwise, a multiframe sync input on RSYNC is treated as a simple frame boundary by the
elastic store. The framer always indicates frame boundaries on the network side of the elastic store via the
RFSYNC output, whether the elastic store is enabled or not. Multiframe boundaries arel always indicated via the
RMSYNC output. If the elastic store is enabled, RMSYNC outputs the multiframe boundary on the backplane side
of the elastic store. When the device is receiving T1 and the backplane is enabled for 2.048MHz operation, the
RMSYNC signal outputs the T1 multiframe boundaries as delayed through the elastic store. When the device is
receiving E1 and the backplane is enabled for 1.544MHz operation, the RMSYNC signal outputs the E1 multiframe
boundaries as delayed through the elastic store.
If the user selects to apply a 2.048MHz clock to the RSYSCLK pin, the user can use the Receive Blank Channel
Select registers (RBCS1:RBCS4) to determine which channels will have the data output at RSER forced to all
ones.
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相關(guān)代理商/技術(shù)參數(shù) |
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| DS26524G | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4-Port E1/T1/J1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS26524G+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4-Port E1/T1/J1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS26524GA4 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS26524GA5 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4-Port E1/T1/J1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS26524GA5+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4-Port E1/T1/J1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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