參數(shù)資料
型號： DS3112DK
廠商： Maxim Integrated Products
文件頁數(shù)： 114/133頁
文件大?。?/td> 0K
描述： KIT DEMO FOR DS3112
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，交叉點開關(guān)/多路復(fù)用器
已用 IC / 零件： DS3112
已供物品： 板，CD
DS3112
81 of 133
26 Bits
1101
Figure 8-1
Bits 8 to 11: Repetitive Pattern Length Bits 5 (RPL0 to RPL3). RPL0 is the LSB and RPL3 is the MSB of a
nibble that describes the how long the repetitive pattern is. The valid range is 17 (0000) to 32 (1111). These bits are
ignored if the receive BERT is programmed for a pseudorandom pattern. To create repetitive patterns less than 17
bits in length, the user must set the length to an integer number of the desired length that is less than or equal to 32.
For example, to create a 6-bit pattern, the user can set the length to 18 (0001) or to 24 (0111) or to 30 (1101).
Repetitive Pattern Length Map
Length
Code
Length
Code
Length
Code
Length
Code
17 Bits
0000
18 Bits
0001
19 Bits
0010
20 Bits
0011
21 Bits
0100
22 Bits
0101
23 Bits
0110
24 Bits
0111
25 Bits
1000
1001
27 Bits
1010
28 Bits
1011
29 Bits
1100
30 Bits
31 Bits
1101
32 Bits
1111
Bit 13: Interrupt Enable for Counter Overflow (IEOF). Allows the receive BERT to cause an interrupt if either
the Bit Counter or the Error Counter overflows (
).
0 = interrupt masked
1 = interrupt enabled
Bit 14: Interrupt Enable for Bit Error Detected (IEBED). Allows the receive BERT to cause an interrupt if a bit
error is detected (Figure 8-1).
Figure 8-1
1 = interrupt enabled
Bit 15: Interrupt Enable for Change of Synchronization Status (IESYNC). Allows the receive BERT to cause
an interrupt if there is a change of state in the synchronization status (i.e., the receive BERT either goes into or out
of synchronization) (
).
0 = interrupt masked
1 = interrupt enabled
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