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參數(shù)資料
| 型號： | DS3174 |
| 英文描述： | Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers |
| 中文描述： | 單/雙/三/四路、DS3/E3單芯片收發(fā)器 |
| 文件頁數(shù)： | 8/232頁 |
| 文件大?。?/td> | 2133K |
| 代理商： | DS3174 |
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DS3171/DS3172/DS3173/DS3174
8 of 230
LIST OF FIGURES
Figure 1-1. LIU External Connections for a DS3/E3 Port of a DS317x Device........................................................... 3
Figure 1-2. DS317x Functional Block Diagram ........................................................................................................... 3
Figure 2-1. Four-Port DS3/E3 Line Card................................................................................................................... 12
Figure 6-1. DS3/E3 SCT Mode.................................................................................................................................. 19
Figure 6-2. DS3/E3 Clear Channel Mode.................................................................................................................. 20
Figure 7-1. HDB3/B3ZS/AMI LIU Mode..................................................................................................................... 22
Figure 7-2. HDB3/B3ZS/AMI Non-LIU Line Interface Mode...................................................................................... 23
Figure 7-3. UNI Line Interface Mode ......................................................................................................................... 24
Figure 8-1. TX Line IO B3ZS Functional Timing Diagram......................................................................................... 36
Figure 8-2. TX Line IO HDB3 Functional Timing Diagram ........................................................................................ 37
Figure 8-3. RX Line IO B3ZS Functional Timing Diagram......................................................................................... 37
Figure 8-4. RX Line IO HDB3 Functional Timing Diagram........................................................................................ 38
Figure 8-5. TX Line IO UNI Functional Timing Diagram............................................................................................ 38
Figure 8-6. RX Line IO UNI Functional Timing Diagram ........................................................................................... 39
Figure 8-7. DS3 Framing Receive Overhead Port Timing......................................................................................... 39
Figure 8-8. E3 G.751 Framing Receive Overhead Port Timing ................................................................................ 39
Figure 8-9. E3 G.832 Framing Receive Overhead Port Timing ................................................................................ 39
Figure 8-10. DS3 Framing Transmit Overhead Port Timing...................................................................................... 40
Figure 8-11. E3 G.751 Framing Transmit Overhead Port Timing ............................................................................. 40
Figure 8-12. E3 G.832 Framing Transmit Overhead Port Timing ............................................................................. 40
Figure 8-13. DS3 SCT Mode Transmit Serial Interface Pin Timing........................................................................... 41
Figure 8-14. E3 G.751 SCT Mode Transmit Serial Interface Pin Timing .................................................................. 41
Figure 8-15. E3 G.832 SCT Mode Transmit Serial Interface Pin Timing .................................................................. 41
Figure 8-16. DS3 SCT Mode Receive Serial Interface Pin Timing............................................................................ 42
Figure 8-17. E3 G.751 SCT Mode Receive Serial Interface Pin Timing ................................................................... 42
Figure 8-18. E3 G.832 SCT Mode Receive Serial Interface Pin Timing ................................................................... 42
Figure 8-19. 16-Bit Mode Write.................................................................................................................................. 43
Figure 8-20. 16-Bit Mode Read ................................................................................................................................. 43
Figure 8-21. 8-Bit Mode Write.................................................................................................................................... 44
Figure 8-22. 8-Bit Mode Read ................................................................................................................................... 44
Figure 8-23. 16-Bit Mode without Byte Swap ............................................................................................................ 45
Figure 8-24. 16-Bit Mode with Byte Swap ................................................................................................................. 45
Figure 8-25. Clear Status Latched Register on Read................................................................................................ 46
Figure 8-26. Clear Status Latched Register on Write................................................................................................ 46
Figure 8-27. RDY Signal Functional Timing Write..................................................................................................... 47
Figure 8-28. RDY Signal Functional Timing Read..................................................................................................... 47
Figure 10-1. Interrupt Structure ................................................................................................................................. 52
Figure 10-2. Internal TX Clock................................................................................................................................... 55
Figure 10-3. Internal RX Clock .................................................................................................................................. 56
Figure 10-4. Example IO Pin Clock Muxing............................................................................................................... 60
Figure 10-5. Reset Sources....................................................................................................................................... 61
Figure 10-6. CLAD Block........................................................................................................................................... 63
Figure 10-7. 8KREF Logic ......................................................................................................................................... 65
Figure 10-8. Performance Monitor Update Logic ...................................................................................................... 68
Figure 10-9. Transmit Error Insert Logic.................................................................................................................... 69
Figure 10-10. Loopback Modes................................................................................................................................. 70
Figure 10-11. ALB Mux.............................................................................................................................................. 70
Figure 10-12. AIS Signal Flow................................................................................................................................... 73
Figure 10-13. Framer Detailed Block Diagram.......................................................................................................... 78
Figure 10-14. DS3 Frame Format.............................................................................................................................. 80
Figure 10-15. DS3 Subframe Framer State Diagram................................................................................................ 80
Figure 10-16. DS3 Multiframe Framer State Diagram............................................................................................... 81
Figure 10-17. G.751 E3 Frame Format ..................................................................................................................... 88
Figure 10-18. G.832 E3 Frame Format ..................................................................................................................... 91
Figure 10-19. MA Byte Format .................................................................................................................................. 91
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS3174N | Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers |
| DS318PIN | Industrial Control IC |
| DS319 | Two-Way Power Divider 10500 MHz |
| DS109333 | Two-Way Power Divider 10500 MHz |
| DS322 | 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS3174+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad DS3/E3 Single Chip Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3174DK | 功能描述:網(wǎng)絡(luò)開發(fā)工具 RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V |
| DS3174N | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad DS3/E3 Single Chip Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3174N+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad DS3/E3 Single Chip Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3177+ | 制造商:Maxim Integrated Products 功能描述:IC TXRX DS3/E3 CSBGA |
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