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參數(shù)資料
| 型號： | DS3234S#T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 7/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RTC W/TCXO 20-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 時鐘/日歷 |
| 特點： | 警報器，閏年，NVSRAM，方波輸出，TCXO/晶體 |
| 存儲容量： | 256B |
| 時間格式： | HH:MM:SS（12/24 小時） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | SPI |
| 電源電壓： | 2 V ~ 5.5 V |
| 電壓 - 電源，電池： | 2 V ~ 3.8 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SOIC W |
| 包裝： | 帶卷 (TR) |
DS3234
Extremely Accurate SPI Bus RTC with
Integrated Crystal and SRAM
____________________________________________________________________
15
Control/Status Register (0Fh/8Fh)
Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit
indicates that the oscillator either is stopped or was
stopped for some period and may be used to judge the
validity of the timekeeping data. This bit is set to logic 1
any time that the oscillator stops. The following are
examples of conditions that can cause the OSF bit to
be set:
1) The first time power is applied.
2) The voltages present on both VCC and VBAT are
insufficient to support oscillation.
3) The EOSC bit is turned off in battery-backed mode.
4) External influences on the crystal (i.e., noise, leak-
age, etc.).
This bit remains at logic 1 until written to logic 0.
Bit 6: Battery-Backed 32kHz Output (BB32kHz). This
bit enables the 32kHz output when powered from VBAT
(provided EN32kHz is enabled). If BB32kHz = 0, the
32kHz output is low when the part is powered by VBAT.
This bit is enabled (logic 1) when power is first applied.
Bits 5 and 4: Conversion Rate (CRATE1 and
CRATE0). These two bits control the sample rate of the
TCXO. The sample rate determines how often the tem-
perature sensor makes a conversion and applies com-
pensation to the oscillator. Decreasing the sample rate
decreases the overall power consumption by decreas-
ing the frequency at which the temperature sensor
operates. However, significant temperature changes
that occur between samples may not be completely
compensated for, which reduce overall accuracy.
These bits are set to logic 0 when power is first applied.
Bit 3: Enable 32kHz Output (EN32kHz). This bit indi-
cates the status of the 32kHz pin. When set to logic 1,
the 32kHz pin is enabled and outputs a 32.768kHz
square-wave signal. When set to logic 0, the 32kHz pin is
low. The initial power-up state of this bit is logic 1, and a
32.768kHz square-wave signal appears at the 32kHz pin
after a power source is applied to the DS3234. This bit is
enabled (logic 1) when power is first applied.
Bit 2: Busy (BSY). This bit indicates the device is busy
executing TCXO functions. It goes to logic 1 when the
conversion signal to the temperature sensor is asserted
and then is cleared when the conversion is complete.
Bit 1: Alarm 2 Flag (A2F). A logic 1 in the alarm 2 flag
bit indicates that the time matched the alarm 2 regis-
ters. If the A2IE bit and INTCN bit are set to logic 1, the
INT/SQW pin is driven low while A2F is active. A2F is
cleared when written to logic 0. This bit can only be
written to logic 0. Attempting to write to logic 1 leaves
the value unchanged.
Bit 0: Alarm 1 Flag (A1F). A logic 1 in the alarm 1 flag
bit indicates that the time matched the alarm 1 regis-
ters. If the A1IE bit and the INTCN bit are set to logic 1,
the INT/SQW pin is driven low while A1F is active. A1F
is cleared when written to logic 0. This bit can only be
written to logic 0. Attempting to write to logic 1 leaves
the value unchanged.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
NAME:
OSF
BB32kHz
CRATE1
CRATE0
EN32kHz
BSY
A2F
A1F
POR*:
1
0
1
0
Control/Status Register (0Fh/8Fh)
*
POR is defined as the first application of power to the device, either VBAT or VCC.
CRATE1
CRATE0
SAMPLE RATE
(seconds)
00
64
0
1
128
1
0
256
1
512
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