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參數(shù)資料
| 型號： | DS3234S#T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 8/21頁 |
| 文件大小： | 0K |
| 描述： | IC RTC W/TCXO 20-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 1,000 |
| 類型： | 時鐘/日歷 |
| 特點： | 警報器，閏年，NVSRAM，方波輸出，TCXO/晶體 |
| 存儲容量： | 256B |
| 時間格式： | HH:MM:SS（12/24 小時） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | SPI |
| 電源電壓： | 2 V ~ 5.5 V |
| 電壓 - 電源，電池： | 2 V ~ 3.8 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SOIC W |
| 包裝： | 帶卷 (TR) |
DS3234
Extremely Accurate SPI Bus RTC with
Integrated Crystal and SRAM
16
____________________________________________________________________
Aging Offset Register (10h/90h)
The aging offset register takes a user-provided value to
add to or subtract from the oscillator capacitor array.
The data is encoded in two’s complement, with bit 7
representing the SIGN bit. One LSB represents the
smallest capacitor to be switched in or out of the
capacitance array at the crystal pins. The aging offset
register capacitance value is added or subtracted from
the capacitance value that the device calculates for
each temperature compensation. The offset register is
added to the capacitance array during a normal tem-
perature conversion, if the temperature changes from
the previous conversion, or during a manual user con-
version (setting the CONV bit). To see the effects of the
aging register on the 32kHz output frequency immedi-
ately, a manual conversion should be performed after
each aging offset register change.
Positive aging values add capacitance to the array,
slowing the oscillator frequency. Negative values
remove capacitance from the array, increasing the
oscillator frequency.
The change in ppm per LSB is different at different tem-
peratures. The frequency vs. temperature curve is shift-
ed by the values used in this register. At +25°C, one
LSB typically provides about 0.1ppm change in fre-
quency. These bits are all set to logic 0 when power is
first applied.
Use of the aging register is not needed to achieve the
accuracy as defined in the EC tables, but could be
used to help compensate for aging at a given tempera-
ture. See the
Typical Operating Characteristics section
for a graph showing the effect of the register on accu-
racy over temperature.
Temperature Registers (11h–12h)
Temperature is represented as a 10-bit code with a res-
olution of 0.25°C and is accessible at location 11h and
12h. The temperature is encoded in two’s complement
format, with bit 7 in the MSB representing the SIGN bit.
The upper 8 bits, the integer portion, are at location 11h
and the lower 2 bits, the fractional portion, are in the
upper nibble at location 12h. Example: 00011001 01b =
+25.25°C. Upon power reset, the registers are set to a
default temperature of 0°C and the controller starts a
temperature conversion.
The temperature is read on initial application of VCC
and once every 64 seconds afterwards. The tempera-
ture registers are updated after each user-initiated con-
version and on every 64-second conversion. The
temperature registers are read-only.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
NAME:
SIGN
DATA
POR*:
000
00
000
Aging Offset (10h/90h)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
NAME:
SIGN
DATA
POR*:
000
00
0
Temperature Register (MSB) (11h)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
NAME:
DATA
0
POR*:
000
00
0
Temperature Register (LSB) (12h)
*
POR is defined as the first application of power to the device, either VBAT or VCC.
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