Note: These pins are always active. NAME TYPE FUNCTION RXPn, RXNn I R" />
參數(shù)資料
型號： DS3254N+
廠商： Maxim Integrated Products
文件頁數(shù)： 3/71頁
文件大小： 0K
描述： IC LIU DS3/E3/STS-1 144-CSBGA
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 160
類型： 線路接口裝置（LIU）
驅(qū)動器/接收器數(shù)： 4/4
規(guī)程： IEEE 1149.1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 144-BGA，CSPBGA
供應(yīng)商設(shè)備封裝： 144-TECSBGA（13x13）
包裝： 托盤
DS3251/DS3252/DS3253/DS3254
11 of 71
Table 6-B. Receiver Pin Descriptions
Note: These pins are always active.
NAME
FUNCTION
RXPn,
RXNn
I
Receiver Analog Inputs. These differential AMI inputs are coupled to the inbound 75
coaxial cable
through a 1:2 step-up transformer (Figure 2-1).
RCLKn
O3
Receiver Clock. The recovered clock is output on the RCLK pin. Recovered data is output on the
RPOS/RDAT and RNEG/RLCV pins on the falling edge of RCLK (RCINV = 0) or the rising edge of
RCLK (RCINV = 1). During a loss of signal (
RLOS = 0), the RCLK output signal is derived from the
LIU’s master clock.
RPOSn/
RDATn
O3
Receiver Positive AMI/Receiver Data. When the receiver is configured to have a bipolar interface
(RBIN = 0), RPOS pulses high for each positive AMI pulse received. When the receiver is configured
to have a binary interface (RBIN = 1), RDAT outputs decoded binary data. RPOS/RDAT is updated
either on the falling edge of RCLK (RCINV = 0) or the rising edge of RCLK (RCINV = 1).
RNEGn/
RLCVn
O3
Receiver Negative AMI/Line-Code Violation. When the receiver is configured to have a bipolar
interface (RBIN = 0), RNEG pulses high for each negative AMI pulse received. When the receiver is
configured to have a binary interface (RBIN = 1), RLCV pulses high to flag code violations. See
Section 8.6 for further details on code violations. RNEG/RLCV is updated either on the falling edge of
RCLK (RCINV = 0) or the rising edge of RCLK (RCINV = 1).
RTSn
I
Receiver Tri-State Enable (Active Low).
RTS tri-states the RPOS/RDAT, RNEG/RLCV, and RCLK
receiver outputs. This feature supports applications requiring LIU redundancy. Receiver outputs from
multiple LIUs can be wire-ORed together, eliminating the need for external switches or muxes. The
receiver continues to operate internally when
RTS is low.
0 = tri-state the receiver outputs
1 = enable the receiver outputs
RLOSn
O
Receiver Loss of Signal (Active Low, Open Drain).
RLOS is asserted upon detection of 175
±75
consecutive zeros in the receive data stream.
RLOS is deasserted when there are no excessive zero
occurrences over a span of 175
±75 clock periods. An excessive zero occurrence is defined as three
or more consecutive zeros in the DS3 and STS-1 modes or four or more zeros in the E3 mode. See
Section 8.5 for more information.
PRBSn
O
PRBS Detector Output. This signal reports the status of the PRBS detector. See Section 11 for
further details.
Table 6-C. Transmitter Pin Descriptions
Note: These pins are always active.
NAME
FUNCTION
TCLKn
I
Transmitter Clock. A DS3 (44.736MHz
±20ppm), E3 (34.368MHz ±20ppm), or STS-1 (51.840MHz
±20ppm) clock should be applied at this signal. Data to be transmitted is clocked into the device at
TPOS/TDAT and TNEG either on the rising edge of TCLK (TCINV = 0) or the falling edge of TCLK
(TCINV = 1). See Section 9 for additional details.
TPOSn/
TDATn
I
Transmitter Positive AMI/Transmitter Data. When the transmitter is configured to have a bipolar
interface (TBIN = 0), a positive pulse is transmitted on the line when TPOS is high. When the
transmitter is configured to have a binary interface (TBIN = 1), the data on TDAT is transmitted after
B3ZS or HDB3 encoding. TPOS/TDAT is sampled either on the rising edge of TCLK (TCINV = 0) or
on the falling edge of TCLK (TCINV = 1).
TNEGn
I
Transmitter Negative AMI. When the transmitter is configured to have a bipolar interface (TBIN = 0),
a negative pulse is transmitted on the line when TNEG is high. When the transmitter is configured to
have a binary interface (TBIN = 1), TNEG is ignored and should be wired either high or low. TNEG is
sampled either on the rising edge of TCLK (TCINV = 0) or on the falling edge of TCLK (TCINV = 1).
TXPn,
TXNn
O3
Transmitter Analog Outputs. These differential AMI outputs are coupled to the outbound 75
coaxial cable through a 2:1 step-down transformer (Figure 2-1). These outputs can be tri-stated using
the
TTS pin or the TTS or TPS configuration bits.
TDMn
O
Transmitter Driver Monitor (Active Low, Open Drain).
TDM reports the status of the transmit driver
monitor. When the monitor detects a faulty transmitter,
TDM is driven low. TDM requires an external
pullup to VDD. See Section 9.6 for more information.
TTSn
I
Transmitter Tri-State Enable (Active Low).
TTS tri-states the transmitter outputs (TXP and TXN).
This feature supports applications requiring LIU redundancy. Transmitter outputs from multiple LIUs
can be wire-ORed together, eliminating external switches. The transmitter continues to operate
internally when
TTS is active.
0 = tri-state the transmitter output driver
1 = enable the transmitter output driver
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS3254N# 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3254N+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3254NA3 制造商:Maxim Integrated Products 功能描述:QUAD ENH DS3/E3 LIU REV A3 IND - Rail/Tube
DS3256 功能描述:網(wǎng)絡(luò)控制器與處理器 IC X6 T3/E3 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3256N 功能描述:網(wǎng)絡(luò)控制器與處理器 IC X6 T3/E3 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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