________________________________________________ DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Rev: 063008
32 of 375
Figure 7-2. 256-Ball, 17mm x 17mm CSBGA Pinout (DS33W41/DS33W11)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
JTCLK
SDA[3]
SDA[10]
SDCS
SDA[12]
SRAS
SWE
SD_CLK
VSS
VDDQ
SDATA[6] SDATA[4]
VDDQ
B
JTRST
SDA[2]
SBA[1]
SBA[0]
SDA[6]
SDA[9]
SCAS
VDD2.5
VREF
SDATA[12] SDATA[13] SDATA[15] SDATA[7]
VSSQ
SDATA[2] SDATA[1]
C
JTMS
SDA[1]
SDA[0]
SD_CLKE
N
SDA[7]
SDA[11]
VSS
VSSQ
SDATA[9] SDATA[11] SDATA[14] SDATA[5] SD_LDQS
VDDQ
SDATA[3] SDATA[0]
D
RDATA1
JTDI
SDA[4]
SDA[5]
SDA[8]
VSSQ
SD_UDM SD_UDQS SDATA[8]
VDDQ
VDD1.8 SDATA[10] SD_LDM
VDDQ
VSSQ
E
RCLK1
JTDO
VDD1.8
VDD2.5
VSSQ
VDD2.5
RST
VDD3.3
AVSS
VDD3.3
RX_CRS1
COL1
VSSQ
SYSCLKI
F
RSYNC1
RVDATA
RVCLK
RVSYNC
AVDD
VSS
VDD3.3
VSS
VDD1.8
RXD[1] /
RXD1[1]
RXD[2] /
RXD1[2]
MDC
VSS
G
RCLK3
RSYNC3
RVDEN
RDATA3
VDD3.3
VSS
RCLK2
RDATA2
VSS
A8
A10
VDD1.8
MDIO
RXD[0] /
RXD1[0]
RX_DV1
RX_CLK1
H
RSYNC4
RDATA4
RCLK4
VSS
DNC
RSYNC2
DNC
VSS
VDD1.8
TXD[3] /
TXD1[3]
RXD[3] /
RXD1[3]
RX_ERR1
HIZ
J
DNC
ALE
CS
WR / RW
INT
MODE
TXD[0] /
TXD1[0]
TXD[2] /
TXD1[2]
SPI_SEL
K
VDD3.3
D0 /
SPI_MISO
D2 /
SPI_CLK
D4
D6 /
SPI_CPHA
A0
A2
A6
A4
TX_EN1
TXD[1] /
TXD1[1]
RXD[7] /
RXD2[3]
L
D1 /
SPI_MOSI
D3
D5 /SPI_
SWAP
A1
A3
A5
A7
A9
TX_ERR1
RXD[6] /
RXD2[2]
M
VDD1.8
TVDATA
TSYNC3
TVCLK
VDD3.3
D7 /
SPI_CPOL
VSS
RMII_SEL TX_CLK1
RXD[5] /
RXD2[1]
N
TVDEN
TDATA4
TXD[4] /
TXD2[0]
RXD[4] /
RXD2[0]
P
VDD3.3
TCLK2
TDATA3
TSYNC4
TCLK4
DCEDTES
TXD[5] /
TXD2[1]
R
VSS
TCLK1
TSYNC1
TVSYNC
TCLK3
VDD1.8
GTX_CLK
TXD[6] /
TXD2[2]
T
DNC
RCLK15
VSS
TDATA1
TDATA2
TSYNC2
REF_CLK
VDD3.3
TXD[7] /
TXD2[3]
Note 1: Shaded pins do not apply to all devices in the product family. See the pin listing for specific pin availability.
Note 2: The TVDEN pin is an input on the DS33W41/DS33W11, and is an output pin on other devices in the product family.