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參數(shù)資料
| 型號(hào)： | DS3503U+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 11/13頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC POT DGTL NV 128TAP 10-MSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 接片： | 128 |
| 電阻（歐姆）： | 5k |
| 電路數(shù)： | 2 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 4 ppm/°C |
| 存儲(chǔ)器類型： | 非易失 |
| 接口： | I²C（設(shè)備位址） |
| 電源電壓： | 2.7 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 100°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-µMAX |
| 包裝： | 帶卷 (TR) |
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DS3503
NV, I2C, Stepper Potentiometer
_______________________________________________________________________________________
7
Step Control Register (SCR)
SCR determines the stepping functionality for the RW
and Y potentiometers (see the
Stepping section). The
five LSBs, bits 4:0, control the STEPCOUNT, which is
the number of steps up and down the wiper moves
when stepping is enabled. Bits 5 and 6 control the
PERIOD, which is the number of pulses of the SYNC pin
required to perform one step.
Setting STEPCOUNT to all zeros disables stepping for the
DS3503. A STEPCOUNT of 1 is an invalid setting. The
DS3503 should not be programmed with a STEPCOUNT
value of 00001.
Control Register (CR)
CR located at register address 02h determines how I2C
data is written to IVR/WR at 00h. When CR is set to a
value of 00h, I2C writes to memory address 00h write to
both WR and IVR. When CR is set to a value of 80h, I2C
writes to memory address 00h write only to WR.
Regardless of the CR setting, all I2C reads of address
00h return the contents of WR.
CR is volatile and powers up as 00h, so I2C writes are
to both the IVR and WR locations. The data that is
stored in EEPROM and SRAM remains unchanged if
the value of CR is changed. Table 3 defines CR.
Stepping
The DS3503 can step the RW output up to WR+STEP-
COUNT and down to WR-STEPCOUNT when stepping
is enabled. Stepping is enabled when a nonzero STEP-
COUNT value is programmed into SCR and pulses are
applied to the SYNC input pin. Stepping is disabled
when STEPCOUNT = 0 or no pulses are applied on the
SYNC input pin. STEPCOUNT = 1 is an invalid setting.
The falling edge of the SYNC pulse updates the out-
puts. The Y potentiometer output is created by adding
to position 40h (code 64 decimal) the same counter
value as is added to WR to form the input to the RW
potentiometer.
The WR value is internally limited (clamped) to a minimum
of STEPCOUNT and maximum of 127 - STEPCOUNT.
When stepping is enabled, the RW wiper position is
controlled by WR plus a counter value (COUNT in the
Functional Diagram). COUNT increments or decre-
ments when the number of SYNC pulses received since
the last COUNT change is equal to PERIOD. SCR bits
6:5 set PERIOD equal to 32, 64, 128, or 256 SYNC puls-
es (see Table 2).
After power-up or after any I2C write to IVR/WR, CR,
or SCR, stepping is initially disabled until 512 plus
BIT
NAME
FUNCTION
4:0
STEPCOUNT
Bit 4 is the MSB; bit 0 is the LSB. These 5 bits define the number of steps in an up or down cycle.
Maximum is 31, minimum is 2. A STEPCOUNT of zero corresponds to a disabled counter.
0, 0: PERIOD = 32 SYNC pulses
0, 1: PERIOD = 64 SYNC pulses
1, 0: PERIOD = 128 SYNC pulses
6:5
PERIOD
1, 1: PERIOD = 256 SYNC pulses
7
—
Reserved
Table 2. Step Control Register Description (01h)
BIT
NAME
FUNCTION
6:0
—
Reserved
7
IVR/WR
ADDRESS
MODE
0: Read WR; write IVR and WR at address 00h.
1: Read WR; write WR at address 00h.
Table 3. Control Register Description (02h)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS3504FP000 | 制造商:Thomas & Betts 功能描述:30A,PLG,3P4W,MG,404,000,3P480V,FC |
| DS3504FP00K | 制造商:Thomas & Betts 功能描述:30A,CON,3P4W,MG,504,00K,3P480V,FC |
| DS3504FP00K/JG63 | 制造商:Thomas & Betts 功能描述:30A,CON,3P4W,504,00K,3P480V,FC,JG63 |
| DS3504FP00K/JG64 | 制造商:Thomas & Betts 功能描述:30A,CON,3P4W,MG,504,3P480V,JG64 |
| DS3504FP00K/JG66 | 制造商:Thomas & Betts 功能描述:30A,CON,3P4W,MG,504,3P480V,JG66 |
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