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參數(shù)資料
| 型號： | DS3503U+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 13/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC POT DGTL NV 128TAP 10-MSOP |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 3,000 |
| 接片： | 128 |
| 電阻（歐姆）： | 5k |
| 電路數(shù)： | 2 |
| 溫度系數(shù)： | 標準值 4 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C（設備位址） |
| 電源電壓： | 2.7 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 100°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 10-µMAX |
| 包裝： | 帶卷 (TR) |
DS3503
NV, I2C, Stepper Potentiometer
_______________________________________________________________________________________
9
Soft Power-On Reset Register (Soft-POR)
By writing register AAh's MSB to 1, a soft power-on
reset (soft-POR) can be generated. When the MSB is
set to 1, the power-up default values of registers 00h,
01h, and 02h are recalled, and the MSB of AAh self-
clears. This soft-POR can be used to recall power-on
settings without cycling power to the DS3503.
I2C Serial Interface Description
I2C Definitions
The following terminology is commonly used to describe
I2C data transfers. (See Figure 2 and the
I2C AC
Electrical Characteristics table for additional information.)
Master device: The master device controls the slave
devices on the bus. The master device generates
SCL clock pulses and START and STOP conditions.
Slave devices: Slave devices send and receive
data at the master’s request.
Bus idle or not busy: Time between STOP and
START conditions when both SDA and SCL are inac-
tive and in their logic-high states.
START condition: A START condition is generated
by the master to initiate a new data transfer with a
slave. Transitioning SDA from high to low while SCL
remains high generates a START condition.
STOP condition: A STOP condition is generated by
the master to end a data transfer with a slave.
Transitioning SDA from low to high while SCL
remains high generates a STOP condition.
Repeated START condition: The master can use a
repeated START condition at the end of one data
transfer to indicate that it will immediately initiate a
new data transfer following the current one. Repeated
STARTs are commonly used during read operations
to identify a specific memory address to begin a data
transfer. A repeated START condition is issued identi-
cally to a normal START condition.
Bit write: Transitions of SDA must occur during the
low state of SCL. The data on SDA must remain valid
and unchanged during the entire high pulse of SCL
plus the setup and hold time requirements. Data is
shifted into the device during the rising edge of the
SCL.
BIT
NAME
FUNCTION
6:0
—
Reserved
7
SOFT POR
0: Default value.
1: Recalls values of IVR, CR, and SCR from EEPROM.
Table 5. Soft Power-On Reset Register Description (AAh)
SCL
NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN).
SDA
STOP
START
REPEATED
START
tBUF
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
tHD:STA
tSP
tSU:STA
tHIGH
tR
tF
tLOW
Figure 2. I2C Timing Diagram
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DS3504FP000 | 制造商:Thomas & Betts 功能描述:30A,PLG,3P4W,MG,404,000,3P480V,FC |
| DS3504FP00K | 制造商:Thomas & Betts 功能描述:30A,CON,3P4W,MG,504,00K,3P480V,FC |
| DS3504FP00K/JG63 | 制造商:Thomas & Betts 功能描述:30A,CON,3P4W,504,00K,3P480V,FC,JG63 |
| DS3504FP00K/JG64 | 制造商:Thomas & Betts 功能描述:30A,CON,3P4W,MG,504,3P480V,JG64 |
| DS3504FP00K/JG66 | 制造商:Thomas & Betts 功能描述:30A,CON,3P4W,MG,504,3P480V,JG66 |
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