I2C, 8-Channel Gamma Buffer with EEPROM _________________________________" />
參數(shù)資料
型號(hào)： DS3508E+T&R
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 8/14頁(yè)
文件大?。?/td> 0K
描述： IC GAMMA BUFFER 8CH 20-TSSOP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
應(yīng)用： TFT-LCD 面板：伽瑪緩沖器
電路數(shù)： 8
電流 - 電源： 2mA
電流 - 輸出 / 通道： 6mA
電壓 - 電源，單路/雙路(±)： 9 V ~ 15.5 V
安裝類型： 表面貼裝
封裝/外殼： 20-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 20-TSSOP
包裝： 帶卷 (TR)
DS3508
I2C, 8-Channel Gamma Buffer with EEPROM
_______________________________________________________________________________________
3
OUTPUT ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +5.5V; VDD = 15.5V, TA = -45°C to +95°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Gamma DAC Resolution
8
Bits
Integral Nonlinearity Error
TA = +25°C (Note 4)
-1.25
+1.25
LSB
Differential Nonlinearity Error
TA = +25°C (Note 5)
-0.5
+0.5
LSB
Output Voltage Range:
GM1–GM4
VHM
VHH
V
Output Voltage Range:
GM5–GM8
VLL
VLM
V
ROUT (GM1–GM8)
ROUT
(Notes 6, 7)
20
k
Amplifier Offset
TA = +25°C (Note 8)
-35
+35
mV
I2C ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +5.5V, TA = -45°C to +95°C, timing referenced to VIL(MAX) and VIH(MIN).) (Figure 4)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCL Clock Frequency
fSCL
(Note 9)
0
400
kHz
Low Period of SCL
tLOW
Measured at VIL
1.3
μs
High Period of SCL
tHIGH
Measured at VIH
0.6
μs
Bus Free Time Between STOP
and START Conditions
tBUF
1.3
μs
START Setup Time
tSU:STA
SCL rising through VIH to SDA falling
through VIH
0.6
μs
Hold Time (Repeated) START
Condition
tHD:STA
SDA falling through VIL to SCL falling
through VIH
0.6
μs
Data Hold Time
tHD:DAT
0
0.9
μs
Data Setup Time
tSU:DAT
100
ns
A0 Setup Time
tSU:A
Before START
0.6
μs
A0 Hold Time
tHD:A
After STOP
0.6
μs
SDA and SCL Rise Time
tR
(Note 10)
20 + (0.1 x CB)
300
ns
SDA and SCL Fall Time
tF
(Note 10)
20 + (0.1 x CB)
300
ns
STOP Setup Time
tSU:STO
0.6
μs
SDA and SCL Capacitive
Loading
CB
(Note 10)
400
pF
EEPROM Write Time
tW
(Note 11)
20
ms
SCL Falling Edge to SDA Output
Data Valid
tAA
SCL falling through VIL to SDA exit
0.3–0.7 x VCC window
900
ns
Output Data Hold
tDH
SCL falling through VIL until SDA in
0.3–0.7 x VCC window
0
ns
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