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參數(shù)資料
| 型號(hào)： | DS72612RP80FPV |
| 廠商： | Renesas Electronics America |
| 文件頁(yè)數(shù)： | 17/226頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC SUPERH MPU ROMLESS 176LQFP |
| 產(chǎn)品培訓(xùn)模塊： | CAN Basics Part-1 CAN Basics Part-2 Electromagnetic Noise Reduction Techniques Part 1 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SuperH® SH7200 |
| 核心處理器： | SH-2A |
| 芯體尺寸： | 32-位 |
| 速度： | 80MHz |
| 連通性： | EBI/EMI，F(xiàn)IFO，I²C，IEBus，SCI，串行聲控 |
| 外圍設(shè)備： | DMA，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 104 |
| 程序存儲(chǔ)器類型： | ROMless |
| RAM 容量： | 32K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b; D/A 2x8b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 176-LQFP |
| 包裝： | 托盤 |
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134
8006K–AVR–10/10
ATtiny24/44/84
If differential channels are selected, the differential gain stage amplifies the voltage difference
between the selected input pair by the selected gain factor, 1x or 20x, according to the setting of
the MUX0 bit in ADMUX. This amplified value then becomes the analog input to the ADC. If sin-
gle ended channels are used, the gain amplifier is bypassed altogether.
The offset of the differential channels can be measure by selecting the same input for both neg-
ative and positive input. Offset calibration can be done for ADC0, ADC3 and ADC7. When ADC0
or ADC3 or ADC7 is selected as both the positive and negative input to the differential gain
amplifier , the remaining offset in the gain stage and conversion circuitry can be measured
directly as the result of the conversion. This figure can be subtracted from subsequent conver-
sions with the same gain setting to reduce offset error to below 1 LSB.
The on-chip temperature sensor is selected by writing the code “100010” to the MUX5:0 bits in
ADMUX register.
The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and
input channel selections will not go into effect until ADEN is set. The ADC does not consume
power when ADEN is cleared, so it is recommended to switch off the ADC before entering power
saving sleep modes.
The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and
ADCL. By default, the result is presented right adjusted, but can optionally be presented left
adjusted by setting the ADLAR bit in ADCSRB.
If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the data
registers belongs to the same conversion. Once ADCL is read, ADC access to data registers is
blocked. This means that if ADCL has been read, and a conversion completes before ADCH is
read, neither register is updated and the result from the conversion is lost. When ADCH is read,
ADC access to the ADCH and ADCL Registers is re-enabled.
The ADC has its own interrupt which can be triggered when a conversion completes. When ADC
access to the data registers is prohibited between reading of ADCH and ADCL, the interrupt will
trigger even if the result is lost.
16.4
Starting a Conversion
A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC.
This bit stays high as long as the conversion is in progress and will be cleared by hardware
when the conversion is completed. If a different data channel is selected while a conversion is in
progress, the ADC will finish the current conversion before performing the channel change.
Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering is
enabled by setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA. The trigger source is
selected by setting the ADC Trigger Select bits, ADTS in ADCSRB (see description of the ADTS
bits for a list of the trigger sources). When a positive edge occurs on the selected trigger signal,
the ADC prescaler is reset and a conversion is started. This provides a method of starting con-
versions at fixed intervals. If the trigger signal still is set when the conversion completes, a new
conversion will not be started. If another positive edge occurs on the trigger signal during con-
version, the edge will be ignored. Note that an Interrupt Flag will be set even if the specific
interrupt is disabled or the Global Interrupt Enable bit in SREG is cleared. A conversion can thus
be triggered without causing an interrupt. However, the Interrupt Flag must be cleared in order to
trigger a new conversion at the next interrupt event.
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