參數(shù)資料
型號(hào)： DS80C320MNG
英文描述： (434.89 k)
中文描述： （434.89十一）
文件頁數(shù)： 13/38頁
文件大小： 434K
代理商： DS80C320MNG
DS80C320/DS80C323
110196 13/38
per cycle scheme on a reset. This allows existing code
with real–time dependencies such as baud rates to
operate properly. If an application needs higher speed
timers or serial baud rates, the timers can be set to run at
the 4 clock rate.
The Clock Control register (CKCON – 8Eh) determines
these timer speeds. When the relevant CKCON bit is a
logic 1, the device uses 4 clocks per cycle to generate
timer speeds. When the control bit is set to a zero, the
device uses 12 clocks for timer speeds. The reset condi-
tion is a 0. CKCON.5 selects the speed of Timer 2.
CKCON.4 selects Timer 1 and CKCON.3 selects Timer
zero. Note that unless a user desires very fast timing, it
is unnecessary to alter these bits. Note that the timer
controls are independent.
POWER FAIL RESET
The DS80C320/DS80C323 incorporates a precision
band–gap voltage reference to determine when V
CC
is
out–of–tolerance. While powering up, internal circuits
will hold the device in a reset state until V
CC
rises above
the V
RST
reset threshold. Once V
CC
is above this level,
the oscillator will begin running. An internal reset circuit
will then count 65536 clocks to allow time for power and
the oscillator to stabilize. The microcontroller will then
exit the reset condition. No external components are
needed to generate a power on reset. During power–
down or during a severe power glitch, as V
CC
falls below
V
RST
, the microcontroller will also generate its own
reset. It will hold the reset condition as long as power
remains below the threshold. This reset will occur auto-
matically, needing no action from the user or from the
software. Refer to the Electrical Specifications for the
exact value of V
RST
.
POWER FAIL INTERRUPT
The same reference that generates a precision reset
threshold can also generate an optional early warning
Power–fail Interrupt (PFI). When enabled by the
application software, this interrupt always has the high-
est priority. On detecting that the V
CC
has dropped
below V
PFW
and that the PFI is enabled, the processor
will vector to ROM address 0033h. The PFI enable is
located in the Watchdog Control SFR (WDCON – D8h).
Setting WDCON.5 to a logic one will enable the PFI. The
application software can also read a flag at WDCON.4.
This bit is set when a PFI condition has occurred. The
flag is independent of the interrupt enable and software
must manually clear it.
WATCHDOG TIMER
For applications that can not afford to run out–of–con-
trol, the DS80C320/DS80C323 incorporates a pro-
grammable Watchdog Timer circuit. It resets the micro-
controller if software fails to reset the Watchdog before
the selected time interval has elapsed. The user selects
one of four time–out values. After enabling the Watch-
dog, software must reset the timer prior to expiration of
the interval, or the CPU will be reset. Both the Watchdog
Enable and the Watchdog Reset bits are protected by a
“Timed Access” circuit. This prevents accidentally
clearing the Watchdog. Time–out values are precise
since they are related to the crystal frequency as shown
below in Table 4. For reference, the time periods at 25
MHz are also shown.
The Watchdog Timer also provides a useful option for
systems that may not require a reset. If enabled, then
512 clocks before giving a reset, the Watchdog will give
an interrupt. The interrupt can also serve as a conve-
nient time–base generator, or be used to wake–up the
processor from Idle mode. The Watchdog function is
controlled in the Clock Control (CKCON – 8Eh), Watch-
dog Control (WDCON – D8h), and Extended Interrupt
Enable (EIE – E8h) SFRs. CKCON.7 and CKCON.6 are
called WD1 and WD0 respectively and are used to
select the Watchdog time–out period as shown in
Table 4.
WATCHDOG TIME–OUT VALUES
Table 4
INTERRUPT
TIME–OUT
2
17
clocks
2
20
clocks
2
23
clocks
2
26
clocks
TIME
(@25 MHz)
5.243 ms
41.94 ms
335.54 ms
2684.35 ms
RESET
TIME–OUT
2
17
+ 512 clocks
2
20
+ 512 clocks
2
23
+ 512 clocks
2
26
+ 512 clocks
TIME
(@25 MHz)
5.263 ms
41.96 ms
335.56 ms
2684.38 ms
WD1
0
0
1
1
WD0
0
1
0
1
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS80C320-MNG 功能描述:8位微控制器 -MCU High-Speed Low-Power RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
DS80C320-MNG+ 功能描述:8位微控制器 -MCU High-Speed Low-Power RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
DS80C320-MNL 功能描述:8位微控制器 -MCU High-Speed Low-Power RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
DS80C320-MNL+ 功能描述:8位微控制器 -MCU High-Speed Low-Power RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
DS80C320-MNR 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:High-Speed Microcontroller User Guide
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