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| 型號： | DS80C320MNG |
| 英文描述： | (434.89 k) |
| 中文描述： | （434.89十一） |
| 文件頁數(shù)： | 7/38頁 |
| 文件大?。?/td> | 434K |
| 代理商： | DS80C320MNG |
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DS80C320/DS80C323
110196 7/38
HIGH–SPEED OPERATION
The DS80C320/DS80C323 is built around a high speed
80C32 compatible core. Higher speed comes not just
from increasing the clock frequency, but from a newer,
more efficient design.
In this updated core, dummy memory cycles have been
eliminated. In a conventional 80C32, machine cycles
are generated by dividing the clock frequency by 12. In
the DS80C320/DS80C323, the same machine cycle is
performed in 4 clocks. Thus the fastest instruction, one
machine cycle, is executed three times faster for the
same crystal frequency. Note that these are identical
instructions. A comparison of the timing differences is
shown in Figure 2. The majority of instructions will see
the full 3 to 1 speed improvement. Some instructions
will get between 1.5 and 2.4 X improvement. Note that
all instructions are faster than the original 80C51.
Table 2 below shows a summary of the instruction set
including the speed.
The numerical average of all opcodes is approximately
a 2.5 to 1 speed improvement. Individual programs will
be affected differently, depending on the actual instruc-
tions used. Speed sensitive applications would make
the most use of instructions that are three times faster.
However, the sheer number of 3 to 1 improved opcodes
makes dramatic speed improvements likely for any
code. When these architecture improvements are com-
bined with 0.8
μ
m CMOS, the result is a single cycle
instruction execution in 160 ns. The Dual Data Pointer
feature also allows the user to eliminate wasted instruc-
tions when moving blocks of memory.
INSTRUCTION SET SUMMARY
All instructions in the DS80C320/DS80C323 perform
the same functions as their 80C32 counterparts. Their
affect on bits, flags, and other status functions is identi-
cal. However, the timing of each instruction is different.
This applies both in absolute and relative number of
clocks.
For absolute timing of real–time events, the timing of
software loops will need to be calculated using the table
below. However, counter/timers default to run at the
older 12 clocks per increment. Therefore, while soft-
ware runs at higher speed, timer–based events need no
modification to operate as before. Timers can be set to
run at 4 clocks per increment cycle to take advantage of
higher speed operation.
The relative time of two instructions might be different in
the new architecture than it was previously. For exam-
ple, in the original architecture, the “MOVX A, @DPTR”
instruction and the “MOV direct, direct” instruction used
two machine cycles or 24 oscillator cycles. Therefore,
they required the same amount of time. In the
DS80C320/DS80C323, the MOVX instruction can be
done in two machine cycles or eight oscillator cycles but
the “MOV direct, direct” uses three machine cycles or 12
oscillator cycles. While both are faster than their original
counterparts, they now have different execution times
from each other. This is because in most cases, the
DS80C320/DS80C323 uses one cycle for each byte.
The user concerned with precise program timing should
examine the timing of each instruction for familiarity with
the changes. Note that a machine cycle now requires
just four clocks, and provides one ALE pulse per cycle.
Many instructions require only one cycle, but some
require five. In the original architecture, all were one or
two cycles except for MUL and DIV.
INSTRUCTION SET SUMMARY
Table 2
Legends:
A
Rn
direct
@Ri
–
–
–
–
Accumulator
Register R7–R0
Internal Register address
Internal Register pointed–to by R0 or R1
(except MOVX)
2’s complement offset byte
direct bit–address
8–bit constant
16–bit constant
16–bit destination address
11–bit destination address
rel
bit
#data
#data 16
addr 16
addr 11
–
–
–
–
–
–
相關PDF資料 |
PDF描述 |
|---|---|
| DS80C323ENG | Microprocessor |
| DS80C323MCG | Microprocessor |
| DS80C323QCG | Microprocessor |
| DS80C390 | Dual CAN High-Speed Microprocessor |
| DS80C390-QNR | Dual CAN High-Speed Microprocessor |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DS80C320-MNG | 功能描述:8位微控制器 -MCU High-Speed Low-Power RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| DS80C320-MNG+ | 功能描述:8位微控制器 -MCU High-Speed Low-Power RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| DS80C320-MNL | 功能描述:8位微控制器 -MCU High-Speed Low-Power RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| DS80C320-MNL+ | 功能描述:8位微控制器 -MCU High-Speed Low-Power RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| DS80C320-MNR | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:High-Speed Microcontroller User Guide |
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