參數(shù)資料
型號(hào)： DS80C390-QNR
廠商： Maxim Integrated Products
文件頁數(shù)： 45/53頁
文件大?。?/td> 0K
描述： IC MPU CAN DUAL HS IND 68-PLCC
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 18
系列： 80C
核心處理器： 8051
芯體尺寸： 8-位
速度： 40MHz
連通性： CAN，EBI/EMI，SIO，UART/USART
外圍設(shè)備： 電源故障復(fù)位，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器類型： ROMless
RAM 容量： 4K x 8
電壓 - 電源 (Vcc/Vdd)： 3.85 V ~ 5.5 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 68-LCC（J 形引線）
包裝： 管件
DS80C390 Dual CAN High-Speed Microprocessor
5 of 53
MOVX CHARACTERISTICS (MULTIPLEXED ADDRESS/DATA BUS) (Note 12)
PARAMETER
SYMBOL
MIN
MAX
UNITS
STRETCH
VALUES
CST (MD2:0)
0.375 tMCS - 5
ns
CST = 0
0.5 tMCS - 5
ns
1
≤ CST ≤ 3
MOVX ALE Pulse Width
tLHLL2
1.5 tMCS - 10
ns
4
≤ CST ≤ 7
0.125 tMCS - 5
ns
CST = 0
0.25tMCS - 5
ns
1
≤ CST ≤ 3
Port 0 MOVX Address,
CE0–4,
PCE0–4 Valid to ALE Low
tAVLL2
1.25 tMCS - 10
ns
4
≤ CST ≤ 7
0.25tMCS-5
ns
CST = 0
0.125 tMCS - 5
ns
1
≤ CST ≤ 3
Address Hold After MOVX
Read/Write
tLLAX2
tLLAX3
1.25 tMCS - 5
ns
4
≤ CST ≤ 7
0.5 tMCS - 6
ns
CST = 0
RD Pulse Width
tRLRH
CST x tMCS - 10
ns
1
≤ CST ≤ 7
0.5 tMCS - 6
ns
CST = 0
WR Pulse Width
tWLWH
CST x tMCS - 10
ns
1
≤ CST ≤ 7
0.5 tMCS - 20
ns
CST = 0
RD Low to Valid Data In
tRLDV
CST x tMCS - 25
ns
1
≤ CST ≤ 7
Data Hold After Read
tRHDX
0
ns
0.25 tMCS - 5
ns
CST = 0
0.5tMCS - 5
ns
1
≤ CST ≤ 3
Data Float After Read
tRHDZ
1.5 tMCS - 5
ns
4
≤ CST ≤ 7
0.625 tMCS - 20
ns
CST = 0
(CST + 0.25) x tMCS - 20
ns
1
≤ CST ≤ 3
ALE Low to Valid Data In
tLLDV
(CST + 1.25) x tMCS - 20
ns
4
≤ CST ≤ 7
0.75 tMCS - 26
ns
CST = 0
(4CST + 0.5) x tMCS - 30
ns
1
≤ CST ≤ 3
Port 0 Address, Port 4 CE, Port 5
PCE to Valid Data In
tAVDV1
(4CST + 2.5) x tMCS - 30
ns
4
≤ CST ≤ 7
0.75 tMCS - 30
ns
CST = 0
(4CST + 0.5) x tMCS - 30
ns
1
≤ CST ≤ 3
Port 2, 4 Address to Valid Data In
tAVDV2
(4CST + 2.5) x tMCS - 30
ns
4
≤ CST ≤ 7
0.125 tMCS - 5
0.125 tMCS + 10
ns
CST =0
0.25tMCS - 5
0.25tMCS + 10
ns
1
≤ CST ≤ 3
ALE Low to
RD or WR Low
tLLWL
1.25 tMCS - 5
1.25 tMCS + 10
ns
4
≤ CST ≤ 7
0.25 tMCS - 11
ns
CST = 0
0.5tMCS - 11
ns
1
≤ CST ≤ 3
Port 0 Address, Port 4 CE, Port 5
PCE to
RD or WR Low
tAVWL1
2.5 tMCS - 11
ns
4
≤ CST ≤ 7
0.375 tMCS - 11
ns
CST = 0
0.625tMCS - 11
ns
1
≤ CST ≤ 3
Port 2, 4 Address to or
WR Low
tAVWL2
2.625 tMCS - 11
ns
4
≤ CST ≤ 7
Data Valid to
WR Transition
tQVWX
-8
ns
0.25 tMCS - 8
ns
CST = 0
0.5tMCS - 10
ns
1
≤ CST ≤ 3
Data Hold After
WR High
tWHQX
1.5 tMCS - 10
ns
4
≤ CST ≤ 7
RD Low to Address Float
tRLAZ
See Note 12
-5
+10
ns
CST = 0
0.25 tMCS - 7
0.25 tMCS + 5
ns
1
≤ CST ≤ 3
RD or WR High to ALE, Port 4 CE
or Port 5 PCE High
tWHLH
1.25 tMCS - 7
1.25 tMCS +10
ns
4
≤ CST ≤ 7
Note 12:
All parameters apply to both commercial and industrial temperature operation. CST is the stretch cycle value determined by the
MD2:0 bits. tMCS is a time period shown in the t
MCS Time Periods table. All signals characterized with load capacitance of 80pF
except Port 0, ALE,
PSEN, RD, and WR with 100pF. Interfacing to memory devices with float times over 25ns can cause bus
contention and an increase in operating current. Specifications assume a 50% duty cycle for the oscillator; port 2 and ALE timing
changes in relation to duty cycle variation. Some AC timing characteristic drawings show the CLK signal, provided to determine the
relative occurrence of events and not the timing of signals relative to the external clock. During the external addressing mode, weak
latches maintain the previously driven value from the processor on Port 0 until Port 0 is overdriven by external memory; and on Port
1, 2 and 4 for one XTAL1 cycle prior to change in output address from Port 1, 2, and 4.
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