參數(shù)資料
型號： DS87C550-QCL+
廠商： Maxim Integrated Products
文件頁數(shù)： 46/49頁
文件大?。?/td> 0K
描述： IC MCU EPROM ADC/PWM HS 68-PLCC
標(biāo)準包裝： 18
系列： 87C
核心處理器： 8051
芯體尺寸： 8-位
速度： 33MHz
連通性： EBI/EMI，SIO，UART/USART
外圍設(shè)備： 電源故障復(fù)位，PWM，WDT
輸入/輸出數(shù)： 55
程序存儲器容量： 8KB（8K x 8）
程序存儲器類型： OTP
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 6x10b
振蕩器型： 外部
工作溫度： 0°C ~ 70°C
封裝/外殼： 68-LCC（J 形引線）
包裝： 管件
DS87C550 EPROM High-Speed Microcontroller with ADC and PWM
6 of 49
PLCC/
CLCC
QFP
SIGNAL NAME
DESCRIPTION
1,
62-68
64-71
P5.0-P5.7
Port 5 - I/O. Port 5 functions as an open-drain 8-bit bi-directional I/O port or
alternately as an interface to the A/D converter. When used for general purpose
I/O, these pins operate in a quasi-bi-directional mode. Writing a logic 1 to these
pins (reset condition) will cause them to tri-state. This allows the pins to serve as
inputs since the tri-state condition can be overdriven by an external device. If a
logic 0 is written to a pin, it is pulled down internally and therefore serves as an
output pin containing a logic 0. Because these pins are open-drain, external pullup
resistors are required to create a logic 1 level when they are used as outputs. As
an alternate function Port 5 pins operate as the analog inputs for the A/D
converter as described below.
Port
Alternate Mode
1
71
P5.0
ADC0
Analog to Digital Converter input channel 0
68
70
P5.1
ADC1
Analog to Digital Converter input channel 1
67
69
P5.2
ADC2
Analog to Digital Converter input channel 2
66
68
P5.3
ADC3
Analog to Digital Converter input channel 3
65
67
P5.4
ADC4
Analog to Digital Converter input channel 4
64
66
P5.5
ADC5
Analog to Digital Converter input channel 5
63
65
P5.6
ADC6
Analog to Digital Converter input channel 6
62
64
P5.7
ADC7
Analog to Digital Converter input channel 7
3-6, 32
33, 38
28, 29
37
74-77
P6.0-P6.5
P6.7
Port 6 - I/O. Port 6 functions as a 7-bit bi-directional I/O port or alternately as an
interface to the PWM and A/D on-board peripherals. As an I/O port, these pins
operate as described in Port 1. Note that P6.6 is not implemented. The alternate
modes of Port 6 are detailed below.
Port
Alternate Function
4
75
P6.0
PWMO0
PWM channel 0 output
5
76
P6.1
PWMO1
PWM channel 1 output
32
28
P6.2
PWMO2
PWM channel 2 output
33
29
P6.3
PWMO3
PWM channel 3 output
6
77
P6.4
PWMC0
PWM0 clock input
38
37
P6.5
PWMC1
PWM1 clock input
3
74
P6.7
STADC
External A/D conversion start signal (active low)
59
60
Avref+
A/D +Reference - Input. Supplies the positive reference voltage for the A/D
converter. This signal should be isolated from digital VCC to prevent noise from
affecting A/D measurements.
58
59
Avref-
A/D -Reference - Input. Supplies the negative reference voltage for the A/D
converter. This signal should be isolated from digital GND to prevent noise from
affecting A/D measurements.
61
63
AVCC
Analog VCC
60
61
AVSS
Analog Ground
3, 21
22, 30
33, 36
43, 44
62, 73
78, 79
NC
NC-Reserved. These pins should not be connected. They are reserved for use
with future devices in this family.
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