參數(shù)資料
型號(hào)： DS87C550-QCL+
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 8/49頁(yè)
文件大小： 0K
描述： IC MCU EPROM ADC/PWM HS 68-PLCC
標(biāo)準(zhǔn)包裝： 18
系列： 87C
核心處理器： 8051
芯體尺寸： 8-位
速度： 33MHz
連通性： EBI/EMI，SIO，UART/USART
外圍設(shè)備： 電源故障復(fù)位，PWM，WDT
輸入/輸出數(shù)： 55
程序存儲(chǔ)器容量： 8KB（8K x 8）
程序存儲(chǔ)器類型： OTP
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 6x10b
振蕩器型： 外部
工作溫度： 0°C ~ 70°C
封裝/外殼： 68-LCC（J 形引線）
包裝： 管件
DS87C550 EPROM High-Speed Microcontroller with ADC and PWM
16 of 49
CLOCK SWITCHING RESTRICTIONS
To ensure clean “glitch-free” switching of the system clock and to ensure that all clocks are running and
stable before they are used, there are minor restrictions on accessing the clock selection bits CD1:0 and
the 4X/ 2X bit.
One restriction is that any change in the CD1 and CD0 bits from a condition other than a 1 0 state (i.e.,
clock divided by 4 mode) must pass through the divide-by-4 state before proceeding to the desired state.
As a specific example, if the clock divisor bits are set to use the frequency multiplier in 4X mode, no
other clock setting is possible until after the CD1:0 bits are set to divide-by-4 mode. After setting clock
divided-by-4 mode, then clock divided by 1024 can be selected by setting CD1 and CD0 to “11b”. Any
attempt to change these bits to a disallowed state will be ignored by the hardware.
There are also some minor restrictions when changing from one clock multiplier to another. Changing the
clock multiplier can only be performed when the Crystal Multiplier Enable bit CTM (PMR.4) is set to 0.
This bit disables the clock multiplication function. However, the CTM bit can only be changed when
CD1 and CD0 are set to divide-by-4 mode (i.e., “10b”) and the ring mode (RNGMD = RCON.2) bit is 0
(discussed later). Changing the clock multiplication factor also requires that the new frequency be stable
prior to effecting the change. The SFR bit CKRDY (RCON.3) indicates the state of the stabilization
timeout. Setting the CTM bit to a 0 from a 1 disables the clock multiplier function, automatically clears
the CKRDY bit, and starts the stabilization timeout.
SYSTEM CLOCK CONTROL Figure 3
During the stabilization period, CKRDY will remain low, and software will be unable to set the CD1:0
bits to select the frequency multiplier. After the stabilization delay, CKRDY will be set to a 1 by
hardware. Note that this bit cannot be set to 1 by software. After hardware sets CKRDY bit, then the
CD1:0 bits can be set to use the clock multiplier function. However, before changing CD1:0, the 4X/ 2X
bit must be set to the desired state. Following this, the CTM bit must be set to 1 to enable the crystal
multiplier. Finally the CD1:0 bits may be set to select the crystal multiplier function. By following this
procedure, the processor is guaranteed to receive a stable, glitch-free clock.
OSCILLATOR-FAIL DETECT
The DS87C550 contains a unique safety mechanism called an on-chip Oscillator-Fail Detect circuit.
When enabled, this circuit causes the processor to be reset if the oscillator frequency falls below 40kHz.
The processor is held in reset until the oscillator frequency rises above 40kHz. In operation, this circuit
can provide a backup for the watchdog timer. Normally, the watchdog timer is initialized so that it will
timeout and will cause a processor reset in the event that the processor loses control. This works perfectly
as long as there is a clock from the crystal or external oscillator, but if this clock fails, there is the
potential for the processor to fail in an uncontrolled and possibly undesirable state. With the use of the
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