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參數(shù)資料
| 型號： | DS90LV804TSQ/NOPB |
| 廠商： | National Semiconductor |
| 文件頁數(shù)： | 10/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC BUFF REPEATER LVDS 4CH 32LLP |
| 產(chǎn)品培訓(xùn)模塊： | High Speed LVDS |
| 標準包裝： | 1 |
| 類型： | 緩沖器 |
| Tx/Rx類型： | LVDS |
| 延遲時間： | 3.2ns |
| 電容 - 輸入： | 3.5pF |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 電流 - 電源： | 140mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-LLP-EP（5x5） |
| 包裝： | 標準包裝 |
| 產(chǎn)品目錄頁面： | 1280 (CN2011-ZH PDF) |
| 其它名稱： | DS90LV804TSQDKR |
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DS90LV804
SNLS195L – SEPTEMBER 2005 – REVISED APRIL 2013
Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Min
Typ(1)
Max
Units
SWITCHING CHARACTERISTICS—LVDS OUTPUTS
tLHT
Differential Low to High Transition
210
300
ps
Time
Use an alternating 1 and 0 pattern at 200 Mbps,
measure between 20% and 80% of VOD
(4)
tHLT
Differential High to Low Transition
210
300
ps
Time
tPLHD
Differential Low to High
2.0
3.2
ns
Propagation Delay
Use an alternating 1 and 0 pattern at 200 Mbps,
measure at 50% VOD between input to output.
tPHLD
Differential High to Low
2.0
3.2
ns
Propagation Delay
tSKD1
Pulse Skew
|tPLHD–tPHLD|
(4)
25
80
ps
tSKCC
Difference in propagation delay (tPLHD or tPHLD)
Output Channel to Channel Skew
50
125
ps
among all output channels(4)
tSKP
Part to Part Skew
Common edge, parts at same temp and VCC
(4)
1.1
ns
tJIT
RJ - Alternating 1 and 0 at 400 MHz(6)
1.1
1.5
psrms
Jitter(5)
DJ - K28.5 Pattern, 800 Mbps(7)
15
35
psp-p
TJ - PRBS 223-1 Pattern, 800 Mbps(8)
30
55
psp-p
tON
Time from EN to OUT± change from TRI-STATE to
LVDS Output Enable Time
300
ns
active.
tOFF
Time from EN to OUT± change from active to TRI-
LVDS Output Disable Time
12
ns
STATE.
(4)
Not production tested. Ensured by statistical analysis on a sample basis at the time of characterization.
(5)
Jitter is not production tested, but ensured through characterization on a sample basis.
(6)
Random Jitter, or RJ, is measured RMS with a histogram including 1500 histogram window hits. The input voltage = VID = 500mV, 50%
duty cycle at 400 MHz, tr = tf = 50ps (20% to 80%).
(7)
Deterministic Jitter, or DJ, is measured to a histogram mean with a sample size of 350 hits. The input voltage = VID = 500mV, K28.5
pattern at 800 Mbps, tr = tf = 50ps (20% to 80%). The K28.5 pattern is repeating bit streams of (0011111010 1100000101).
(8)
Total Jitter, or TJ, is measured peak to peak with a histogram including 3500 window hits. Stimulus and fixture Jitter has been
subtracted. The input voltage = VID = 500mV, 2
23-1 PRBS pattern at 800 Mbps, t
r = tf = 50ps (20% to 80%).
Typical Application
4
Copyright 2005–2013, Texas Instruments Incorporated
Product Folder Links: DS90LV804
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