參數(shù)資料
型號: DSD1792DB
廠商: Texas Instruments
文件頁數(shù): 30/57頁
文件大?。?/td> 0K
描述: IC 24BIT STEREO AUD DAC 28-SSOP
產(chǎn)品培訓(xùn)模塊: Data Converter Basics
標(biāo)準(zhǔn)包裝: 47
位數(shù): 24
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 模擬和數(shù)字
功率耗散(最大): 335mW
工作溫度: -25°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 28-SSOP
包裝: 管件
輸出數(shù)目和類型: 4 電流,單極
采樣率(每秒): 200k
產(chǎn)品目錄頁面: 902 (CN2011-ZH PDF)
其它名稱: 296-15310-5
DSD1792
SLES067B MARCH 2003 REVISED NOVEMBER 2006
www.ti.com
36
Functions Available in the External Digital Filter Mode
The external digital filter mode allows access to the majority of the DSD1792 mode control functions.
The following table shows the register mapping available when the external digital filter mode is selected, along
with descriptions of functions which are modified when using this mode selection.
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 16
R/W
0
1
0
Register 17
R/W
0
1
0
1
Register 18
R/W
0
1
0
1
0
FMT2
FMT1
FMT0
Register 19
R/W
0
1
0
1
REV
OPE
DFMS
INZD
Register 20
R/W
0
1
0
1
0
SRST
0
1
MONO
CHSL
OS1
OS0
Register 21
R/W
0
1
0
1
0
1
PCMZ
Register 22
R
0
1
0
1
0
ZFGR
ZFGL
NOTE: 1: Bit is required for selection of external digital filter mode.
–: Function is disabled. No operation even if data bit is set
FMT[2:0]: Audio Data Format Selection
Default value: 000
FMT[2:0]
Audio Data Format Select
000
16-bit right-justified format (default)
001
20-bit right-justified format
010
24-bit right-justified format
Other
N/A
OS[1:0]: Delta-Sigma Modulator Oversampling Rate Selection
Default value: 00
OS[1:0]
Operation Speed Select
00
8 times WDCK (default)
01
4 times WDCK
10
16 times WDCK
11
Reserved
The effective oversampling rate is determined by the oversampling performed by both the external digital filter
and the delta-sigma modulator. For example, if the external digital filter is 8
× oversampling, and the user selects
OS[1:0] = 00, then the delta-sigma modulator oversamples by 8
×, resulting in an effective oversampling rate
of 64
×. The 16× WDCK oversampling rate is not available above a 100-kHz sampling rate. If the oversampling
rate selected is 16
× WDCK, the system clock frequency must be over 256 fS.
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