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參數(shù)資料
| 型號： | DSD1792DB |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 42/57頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 24BIT STEREO AUD DAC 28-SSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Basics |
| 標(biāo)準(zhǔn)包裝： | 47 |
| 位數(shù)： | 24 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 335mW |
| 工作溫度： | -25°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 4 電流，單極 |
| 采樣率（每秒）： | 200k |
| 產(chǎn)品目錄頁面： | 902 (CN2011-ZH PDF) |
| 其它名稱： | 296-15310-5 |
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DSD1792
SLES067B MARCH 2003 REVISED NOVEMBER 2006
www.ti.com
47
Audio Fields
The audio field is 32 bits in length and the audio data is transferred MSB first, so the other fields must be stuffed
with 0s as shown in the following example.
31
16
12
8
7
4 3
0
Audio data
MSB
24 bits
LSB
All 0s
TDMCA Register Requirements
TDMCA mode requires device ID and audio channel information, previously described. The OPE bit in register
19 indicates audio channel availability and register 23 indicates the device ID. Register 23 is used only in the
TDMCA mode. See the mode control register map (Table 3).
Register Write/Read Operation
The command supports register write and read operations. If the command requests to read one register, the
read data is transferred on DO during the data phase of the timing cycle. The DI signal can be retrieved at the
positive edge of BCK, and the DO signal is driven at the negative edge of BCK. DO is activated one BCK cycle
early to compensate for the output delay caused by high impedance. Figure 57 shows the TDMCA write and
read timing.
BCK
DI
DO
DOEN
(Internal)
1 BCK Early
Read Mode and Proper Register ID
Write Data Retrieved, if Write Mode
Read Data Driven, if Read Mode
Register ID Phase
Data Phase
Figure 57. TDMCA Write and Read Operation Timing
TDMCA-Mode Operation
DCO specifies the owner of the next audio channel in TDMCA-mode operation. When a device retrieves its own
audio channel data, DCO goes HIGH during the last audio channel period. Figure 58 shows the DCO output
timing in TDMCA-mode operation. The host controller ignores the behavior of DCI and DCO. DCO indicates
the last audio channel of each device. Therefore, DCI means the next audio channel is allocated.
If some devices are skipped due to no active audio channel, the skipped devices must notify the next device
that the DCO will be passed through the next DCI. Figure 59 and Figure 60 show DCO timing with skip
operation. Figure 61 shows the ac timing of the daisy chain signals.
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