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參數(shù)資料
| 型號： | DSP102KP |
| 英文描述： | TVS 400W 6.0V UNIDIRECT SMA |
| 中文描述： | DSP兼容采樣單/雙模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 11/22頁 |
| 文件大?。?/td> | 252K |
| 代理商： | DSP102KP |
DSP101/102
11
During the internal successive approximation conversion
process, the conversion results are shifted into the input shift
registers of the output stage on the DSP102. A new convert
command latches that data into the 18-bit parallel latches
shown. The internal signal that also generates the Sync
pulse, labeled “Shift/Load” in Figure 4, synchronously loads
the conversion data into the output shift register on the rising
edge of XCLK. The conversion results are then clocked out
of the shift register on subsequent rising edges of XCLK.
DATA TRANSFER CLOCK
XCLK is the data transfer clock, or bit clock, for the system,
and is an input for the DSP101 or DSP102. This input is
TTL- and 74HC-level compatible. The serial data and SYNC
outputs are synchronized internally to this clock, with data
valid on the rising edge of XCLK, per the timing shown in
Figure 1. Data input on pin 18 (TAG) on the DSP101, or on
pins 18 and 19 on the DSP102 (TAGA and TAGB), will be
clocked into the output shift register on the rising edge of
XCLK, as discussed in the Tag Feature section.
CONVERSION CLOCK
The analog-to-digital converter sections in the DSP101 and
DSP102 were designed to provide accurate conversions
under worst case conditions of supplies, temperatures, etc.
In order to achieve a full 200kHz sampling capability, they
were designed to use a 33% duty cycle conversion clock
(CLKIN on pin 10) as shown in Figure 1. The clock is LOW
FIGURE 6. DSP101 or DSP102 Power Supply Connections.
FIGURE 5. DSP101 or DSP102 Conversion Clock Circuit.
To other
DSP102's CLKIN for
synchronous operation
1M
Crystal is CTS Knight MP122 12.288MHz,
20pF load, series resonant mode.
12.288MHz
÷3
SAR Clock
Control
10pF
10
11
DSP101 or DSP102
CLKOUT
OSC2
OSC1
13
14
10pF
CLKIN
long enough for internal analog circuitry to settle suffi-
ciently between bit decisions to insure rated accuracy. Bit
decisions in the A/D are then made on the rising edge of
CLKIN.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
10μF
10μF
0.1μF
VPOTA
AGND
REF
VPOTB
10μF
DSP101 or DSP102
+
+
+
+
10μF
0.01μF
–5V Analog
+5V Analog
+5V Digital
V –
V +
DGND
DGND
V
D
= Analog Ground
= Digital Ground
(1)
(1)
NOTES: (1) Pin 1 and pin 26 must be bypassed with 10μF tantalum capacitors, on both the DSP101 and DSP102.
(2) Protection from power supply momentary overrange.
10
(2)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSP-102M | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:DIA SURGE SUPPRESSOR (DSS) |
| DSP105 | 制造商:TDK-Lambda Corporation 功能描述:AC/DC Power Supply Single-OUT 5V 1.5A 7.5W 制造商:TDK-Lambda Corporation 功能描述:AC/DC PS SGL-OUT 5V 1.5A 7.5W - Bulk 制造商:TDK 功能描述:PWR SUP DIN RAIL 5V 7.5W 1.5A 制造商:TDK-Lambda 功能描述:AC/DC Power Supply Single-OUT 5V 1.5A 7.5W |
| DSP10-5 | 功能描述:DIN導(dǎo)軌式電源 7.5W 5V 1.5A DIN Rail 115-230VAC RoHS:否 制造商:Mean Well 產(chǎn)品:Linear Supplies 商用/醫(yī)用:Commercial 輸出功率額定值:960 W 輸入電壓:180 VAC to 264 VAC, 254 VDC to 370 VDC 輸出端數(shù)量:1 輸出電壓（通道 1）:48 V 輸出電流（通道 1）: 輸出電壓（通道 2）: 輸出電流（通道 2）: 輸出電壓（通道 3）: 輸出電流（通道 3）: 尺寸:150 mm L x 110 mm W |
| DSP10-5 | 制造商:TDK-Lambda Corporation 功能描述:Switch Mode Power Supply |
| DSP10G | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
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