參數(shù)資料
型號(hào)： DSP102KP
英文描述： TVS 400W 6.0V UNIDIRECT SMA
中文描述： DSP兼容采樣單/雙模擬數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù)： 13/22頁(yè)
文件大?。?/td> 252K
代理商： DSP102KP
DSP101/102
13
20 (SOUTA) containing data for both input channels in two
16-bit words. Referring to Figure 1, the first 16 bits of data
will be the results for channel A, followed by 16 bits of
information for channel B. The data will be transferred MSB
first. A convert command at time (t) will initiate the trans-
mission of the results of the conversion initiated at time
(t – 1).
From the descriptions above of the internal shift registers
shown in Figure 4, it can be seen that the DSP102 in the
Cascade Mode actually continues to shift out data after the
32nd bit of the data word. The next two bits clocked out will
be the last two data bits from the full 18-bit conversion on
channel B, after which the information output on SOUTA
will be the information clocked into TAGB 35 bit clock
cycles earlier.
In the Cascade mode on the DSP102, SOUTB will still
output channel B conversion data and tag data as usual.
ANALOG PERFORMANCE
LINEARITY
The DSP101 and DSP102 are optimized for signal process-
ing applications with wide dynamic range requirements.
Linearity is trimmed for best performance in the range
around 0V, which is critical for handling low amplitude
signals. The DSP101 and DSP102 typically have integral
and differential non-linearity below
±
0.003% in the input
range of
±
0.7V, with there being no missing codes at the
14-bit level in this range. Over the full
±
2.75V input range,
the largest non-linearities are centered around the bit #2
transition points at +1.375V and –1.375V levels.
NOISE AND BIPOLAR ZERO ERROR
The equivalent input noise and bipolar zero error of the
DSP101 and DSP102 is shown in the typical performance
section for both channels on a DSP102. The inputs to both
channels were grounded, and the results of 5,000 conver-
sions was recorded. The data shown is binned at the 16-bit
level. The noise results from all sources in the circuit,
including clocks, reference noise, etc.
In a theoretically ideal converter with no offset and no noise,
the results of all 5,000 conversion for each channel would lie
in the bin corresponding to bipolar zero, code 0000. The
typical DSP101 or DSP102 will have offset errors in the
range of 1 to 2mV, and the two channels on the DSP102 will
be matched closer than 2mV. The DSP102 shown in the
typical performance section has the worst offset, –0.8mV,
on channel A, with channel B being less than 1mV different,
and the three sigma noise on either channel being less than
250
μ
V.
INPUT BANDWIDTH
From the typical performance curves, it can be seen that
there is very little degradation in Signal-to-(Noise + Distor-
tion) for input signals up to 100kHz. The wideband sampling
input typically maintains a 60dB Signal-to-(Noise + Distor-
tion) Ratio undersampling 500kHz input signals.
LAYOUT CONSIDERATIONS
Because of the high resolution, linearity and speed of the
DSP101 and DSP102, system design problems such as
ground path resistance, contact resistance and power supply
quality become very important.
FIGURE 8. DSP101 or DSP102 Optional MSB and Offset Adjust.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
0.1μF
VPOTA
MSBA
VOSA
REF
VPOTB
MSBB
VOSB
150k
25k
10μF
47k
25k
+
47k
25k
10μF
150k
25k
+
DSP101 or DSP102
(1)
47k
0.01μF
0.01μF
0.01μF
47k
0.01μF
Leave out on DSP101
(1)
NOTE: (1) On DSP101, pins 23 and 24 are
not internally connected. Pin 26 must still be
bypassed with the 10μF Tantalum capacitor.
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