參數(shù)資料
型號： DSP56321VL200R2
廠商： Freescale Semiconductor
文件頁數(shù)： 1/84頁
文件大?。?/td> 0K
描述： IC DSP 24BIT 200MHZ 196-MAPBGA
標準包裝： 750
系列： DSP56K/Symphony
類型： 定點
接口： 主機接口，SSI，SCI
時鐘速率： 200MHz
非易失內(nèi)存： ROM（576 B）
芯片上RAM： 576kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.60V
工作溫度： -40°C ~ 100°C
安裝類型： 表面貼裝
封裝/外殼： 196-FBGA
供應(yīng)商設(shè)備封裝： 196-MAPBGA（15x15）
包裝： 帶卷 (TR)
Freescale Semiconductor
Technical Data
DSP56321
Rev. 11, 2/2005
Freescale Semiconductor, Inc., 2001, 2005. All rights reserved.
DSP56321
24-Bit Digital Signal Processor
The Freescale DSP56321, a member of the DSP56300 DSP family, supports networking, security encryption, and
home entertainment using a high-performance, single-clock-cycle-per- instruction engine (DSP56000 code-
compatible), a barrel shifter, 24-bit addressing, an instruction cache, and a direct memory access (DMA) controller
(see Figure 1).
The DSP56321 offers 275 million multiply- accumulates per second (MMACS) performance, attaining 550
MMACS when the EFCOP is in use. It operates with an internal 275 MHz clock with a 1.6 volt core and
independent 3.3 volt input/output (I/O) power. By operating in parallel with the core, the EFCOP provides overall
enhanced performance and signal quality with no impact on channel throughput or total channel support. This
device is pin-compatible with the Freescale DSP56303, DSP56L307, DSP56309, and DSP56311.
Figure 1. DSP56321 Block Diagram
YAB
XAB
PAB
YDB
XDB
PDB
GDB
MODB/IRQB
MODC/IRQC
10
MODD/IRQD
DSP56300
6
16
24-Bit
24
18
DDB
DAB
Peripheral
Core
YM
_
E
B
XM
_
E
B
PM
_
E
B
PI
O
_
E
B
Expansion Area
6
5
3
RESET
MODA/IRQA
PINIT/NMI
EXTAL
XTAL
Address
Control
Data
Address
Generation
Unit
Six Channel
DMA Unit
Program
Interrupt
Controller
Program
Decode
Controller
Program
Address
Generator
Data ALU
24
× 24 + 56 →56-bit MAC
Two 56-bit Accumulators
56-bit Barrel Shifter
Power
Management
External
Bus
Interface
and
I - Cache
Control
Memory Expansion Area
DE
Program
RAM
32 K
× 24 bits
X Data
RAM
80 K
× 24 bits
Y Data
RAM
80 K
× 24 bits
External
Address
Bus
Switch
SCI
EFCOP
ESSI
HI08
Triple
Timer
or
31 K
× 24 bits
Instruction
Cache
1024
× 24 bits
Bootstrap
ROM
and
OnCE
JTAG
PLL
Clock
Generator
Internal
Data
Bus
Switch
External
Data
Bus
Switch
The DSP56321 is intended
for applications requiring a
large amount of internal
memory, such as networking
and wireless infrastructure
applications. The onboard
EFCOP can accelerate
general filtering applications,
such as echo-cancellation
applications, correlation, and
general-purpose convolution-
based algorithms.
What’s New?
Rev. 11 includes the following
changes:
Adds lead-free packaging and
part numbers.
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