參數(shù)資料
型號(hào)： DSP56857BUE
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： 16-bit Digital Signal Controllers
中文描述： 16位數(shù)字信號(hào)控制器
文件頁(yè)數(shù)： 29/53頁(yè)
文件大?。?/td> 680K
代理商： DSP56857BUE
Reset, Stop, Wait, Mode Select, and Interrupt Timing
56857 Technical Data, Rev. 6
Freescale Semiconductor
29
4.6 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Table 4-6 PLL Timing
Operating Conditions: V
SS
= V
SSIO
= V
SSA
= 0 V, V
DD
= 1.62-1.98V, V
DDIO
= V
DDA
=
3.0–3.6V, T
A
= –40
°
to +120
°
C, C
L
≤
50pF, f
op
= 120MHz
Characteristic
Symbol
Min
Typ
Max
Unit
External reference crystal frequency for the PLL
1
1.
An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly.
The PLL is optimized for 4MHz input crystal.
f
osc
2
4
4
MHz
PLL output frequency
f
clk
40
—
240
MHz
PLL stabilization time
2
2.
This is the minimum time required after the PLL setup is changed to ensure reliable operation.
t
plls
—
1
10
ms
Table 4-7 Reset, Stop, Wait, Mode Select, and Interrupt Timing
1, 2
Operating Conditions: V
SS
= V
SSIO
= V
SSA
= 0 V, V
DD
= 1.62-1.98V, V
DDIO
= V
DDA
=
3.0–3.6V, T
A
= –40
°
to +120
°
C, C
L
≤
50pF, f
op
= 120MHz
1.
In the formulas, T = clock cycle. For f
op
= 120MHz operation and f
ipb
= 60MHz, T = 8.33ns.
Parameters listed are guaranteed by design.
2.
Characteristic
Symbol
Typ Min
Typ
Max
Unit
See Figure
Minimum RESET Assertion Duration
3
3.
At reset, the PLL is disabled and bypassed. The part is then put into Run mode and t
clk
assumes the period of the source clock,
t
xtal
, t
extal
or t
osc
.
This interrupt instruction fetch is visible on the pins only in Mode 3.
t
RA
30
—
ns
4-10
Edge-sensitive Interrupt Request Width
t
IRW
1T + 3
—
ns
4-11
IRQA, IRQB Assertion to General Purpose Output Valid,
caused by first instruction execution in the interrupt
service routine
t
IG
18T
—
ns
4-12
IRQA Width Assertion to Recover from Stop State
t
IW
2T
—
ns
4-13
Delay from IRQA Assertion to Fetch of first instruction
(exiting Stop)
4
Fast
5
Normal
6, 7
4.
5.
Fast stop mode:
Fast stop recovery applies when external clocking is in use (direct clocking to XTAL) or when fast stop mode recovery is request-
ed (OMR bit 6 is set to 1). In both cases the PLL and the master clock are unaffected by stop mode entry. Recovery takes one less
cycle and t
clk
will continue with the same value it had before stop mode was entered.
6.
Normal stop mode:
As a power saving feature, normal stop mode disables and bypasses the PLL. Stop mode will then shut down the master clock,
recovery will take an extra cycle (to restart the clock), and t
clk
will resume at the input clock source rate.
7.
ET = External Clock period; for an external crystal frequency of 4MHz, ET=250ns.
t
IF
—
—
13T
25ET
ns
ns
4-13
RSTO pulse width
7
normal operation
internal reset mode
t
RSTO
128ET
8ET
—
—
—
—
4-14
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