參數(shù)資料
型號: DSP56857BUE
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: 16-bit Digital Signal Controllers
中文描述: 16位數(shù)字信號控制器
文件頁數(shù): 34/53頁
文件大?。?/td> 680K
代理商: DSP56857BUE
56857 Technical Data, Rev. 6
34
Freescale Semiconductor
4.8 Serial Peripheral Interface (SPI) Timing
1. Parameters listed are guaranteed by design.
Table 4-9 SPI Timing
1
Operating Conditions: V
SS
= V
SSIO
= V
SSA
= 0 V, V
DD
= 1.62-1.98V, V
DDIO
= V
DDA
=
3.0–3.6V, T
A
= –40
°
to +120
°
C, C
L
50pF, f
op
= 120MHz
Characteristic
Symbol
Min
Max
Unit
See
Figure
Cycle time
Master
Slave
t
C
25
25
ns
ns
4-21
,
4-22
,
4-23
,
4-24
Enable lead time
Master
Slave
t
ELD
12.5
ns
ns
4-24
Enable lag time
Master
Slave
t
ELG
12.5
ns
ns
4-24
Clock (SCLK) high time
Master
Slave
t
CH
9
12.5
ns
ns
4-21
,
4-22
,
4-23
,
4-24
Clock (SCLK) low time
Master
Slave
t
CL
12
12.5
ns
ns
4-24
Data set-up time required for inputs
Master
Slave
t
DS
10
2
ns
ns
4-21
,
4-22
,
4-23
,
4-24
Data hold time required for inputs
Master
Slave
t
DH
0
2
ns
ns
4-21
,
4-22
,
4-23
,
4-24
Access time (time to data active from high-impedance state)
Slave
t
A
5
15
ns
ns
4-24
Disable time (hold time to high-impedance state)
Slave
t
D
2
9
ns
ns
4-24
Data valid for outputs
Master
Slave (after enable edge)
t
DV
2
14
ns
ns
4-21
,
4-22
,
4-23
,
4-24
Data invalid
Master
Slave
t
DI
0
0
ns
ns
4-21
,
4-22
,
4-23
,
4-24
Rise time
Master
Slave
t
R
11.5
10.0
ns
ns
4-21
,
4-22
,
4-23
,
4-24
Fall time
Master
Slave
t
F
9.7
9.0
ns
ns
4-21
,
4-22
,
4-23
,
4-24
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