參數(shù)資料
型號(hào)： DSP56858FVE
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 13/64頁(yè)
文件大?。?/td> 0K
描述： IC DSP 16BIT 120MHZ 144-LQFP
標(biāo)準(zhǔn)包裝： 60
系列： 568xx
核心處理器： 56800E
芯體尺寸： 16-位
速度： 120MHz
連通性： EBI/EMI，SCI，SPI，SSI
外圍設(shè)備： DMA，POR，WDT
輸入/輸出數(shù)： 47
程序存儲(chǔ)器容量： 80KB（40K x 16）
程序存儲(chǔ)器類型： SRAM
RAM 容量： 24K x 16
電壓 - 電源 (Vcc/Vdd)： 1.62 V ~ 1.98 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 144-LQFP
包裝： 托盤
56858 Technical Data, Rev. 6
20
Freescale Semiconductor
MISO
GPIOF0
B2
1
Input/Output
Input/Output
SPI Master In/Slave Out (MISO)—This serial data pin is an input to a
master device and an output from a slave device. The MISO line of a
slave device is placed in the high-impedance state if the slave device
is not selected. The driver on this pin can be configured as an
open-drain driver by the SPI’s Wired-OR mode (WOM) bit when this
pin is configured for SPI operation.
Port F GPIO (0)—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as input or output pin.
MOSI
GPIOF1
C3
2
Input/
Output (Z)
Input/Output
SPI Master Out/Slave In (MOSI)—This serial data pin is an output
from a master device and an input to a slave device. The master
device places data on the MOSI line a half-cycle before the clock edge
that the slave device uses to latch the data. The driver on this pin can
be configured as an open-drain driver by the SPI’s WOM bit when this
pin is configured for SPI operation.
Port F GPIO (1)—This pin is a General Purpose I/O (GPIO) pin that
can be individually programmed as input or output pin.
SCK
GPIOF2
C2
3
Input/Output
Input/Output
SPI Serial Clock (SCK)—This bidirectional pin provides a serial bit
rate clock for the SPI. This gated clock signal is an input to a slave
device and is generated as an output by a master device. Slave
devices ignore the SCK signal unless the SS pin is active low. In both
master and slave SPI devices, data is shifted on one edge of the SCK
signal and is sampled on the opposite edge where data is stable. The
driver on this pin can be configured as an open-drain driver by the
SPI’s WOM bit when this pin is configured for SPI operation. When
using Wired-OR mode, the user must provide an external pull-up
device.
Port F GPIO (2)—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as input or output pin.
SS
GPIOF3
D2
4
Input
Input/Output
SPI Slave Select (SS)—This input pin selects a slave device before a
master device can exchange data with the slave device. SS must be
low before data transactions and must stay low for the duration of the
transaction. The SS line of the master must be held high.
Port F GPIO (3)—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as input or output pin.
XTAL
H2
27
Input/Output
Crystal Oscillator Output (XTAL)—This output connects the internal
crystal oscillator output to an external crystal. If an external clock
source other than a crystal oscillator is used, XTAL must be used as
the input.
EXTAL
G3
28
Input
External Crystal Oscillator Input (EXTAL)—This input should be
connected to an external crystal. If an external clock source other than
a crystal oscillator is used, EXTAL must be tied off. See Section 4.5.2
CLKO
L3
37
Output
Clock Output (CLKO)—This pin outputs a buffered clock signal.
When enabled, this signal is the system clock divided by four.
Table 3-1 56858 Signal and Package Information for the 144-pin LQFP and MAPBGA
Signal
Name
BGA
Pin No.
LQFP
Pin No.
Type
Description
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