參數(shù)資料
型號: DSP56858FVE
廠商: Freescale Semiconductor
文件頁數(shù): 4/64頁
文件大?。?/td> 0K
描述: IC DSP 16BIT 120MHZ 144-LQFP
標(biāo)準(zhǔn)包裝: 60
系列: 568xx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 120MHz
連通性: EBI/EMI,SCI,SPI,SSI
外圍設(shè)備: DMA,POR,WDT
輸入/輸出數(shù): 47
程序存儲器容量: 80KB(40K x 16)
程序存儲器類型: SRAM
RAM 容量: 24K x 16
電壓 - 電源 (Vcc/Vdd): 1.62 V ~ 1.98 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 144-LQFP
包裝: 托盤
56858 Technical Data, Rev. 6
12
Freescale Semiconductor
D0
H7
81
Input/
Output(Z)
Data Bus (D0-D15)—These pins provide the bidirectional data for
external program or data memory accesses.
D1
G7
94
D2
F9
95
D3
F10
96
D4
F11
97
D5
E10
98
D6
D7
120
D7
B7
121
D8
E7
122
D9
F8
123
D10
F7
124
D11
D5
137
D12
B4
138
D13
C4
142
D14
F6
143
D15
B3
144
RD
D3
8
Output
Read Enable (RD) — is asserted during external memory read cycles.
This signal is pulled high during reset.
WR
D4
9
Output
Write Enable (WR) —is asserted during external memory write cycles.
This signal is pulled high during reset.
CS0
GPIOA0
H8
83
Output
Input/Output
External Chip Select (CS0)—This pin is used as a dedicated GPIO.
Port A GPIO (0) —This pin is a General Purpose I/O (GPIO) pin when
not configured for host port usage.
CS1
GPIOA1
H9
84
Output
Input/Output
External Chip Select (CS1)—This pin is used as a dedicated GPIO.
Port A GPIO (1) —This pin is a General Purpose I/O (GPIO) pin when
not configured for host port usage.
CS2
GPIOA2
H11
85
Output
Input/Output
External Chip Select (CS2)—This pin is used as a dedicated GPIO.
Port A GPIO (2) —This pin is a General Purpose I/O (GPIO) pin when
not configured for host port usage.
CS3
GPIOA3
H10
86
Output
Input/Output
External Chip Select (CS3)—This pin is used as a dedicated GPIO.
Port A GPIO (3)—This pin is a General Purpose I/O (GPIO) pin when
not configured for host port usage.
Table 3-1 56858 Signal and Package Information for the 144-pin LQFP and MAPBGA
Signal
Name
BGA
Pin No.
LQFP
Pin No.
Type
Description
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