參數(shù)資料
型號： DSP56F801FA60E
廠商： Freescale Semiconductor
文件頁數(shù)： 22/48頁
文件大?。?/td> 0K
描述： IC DSP 60MHZ 16KB FLASH 48-LQFP
標(biāo)準(zhǔn)包裝： 250
系列： 56F8xx
核心處理器： 56800
芯體尺寸： 16-位
速度： 60MHz
連通性： SCI，SPI
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 11
程序存儲器容量： 20KB（10K x 16）
程序存儲器類型： 閃存
RAM 容量： 2K x 16
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 48-LQFP
包裝： 托盤
Reset, Stop, Wait, Mode Select, and Interrupt Timing
56F801 Technical Data, Rev. 17
Freescale Semiconductor
29
3.6 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Table 3-11 Reset, Stop, Wait, Mode Select, and Interrupt Timing1, 5
Operating Conditions: V
SS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF
1.
In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns.
Characteristic
Symbol
Min
Max
Unit
See
RESET Assertion to Address, Data and Control
Signals High Impedance
tRAZ
—21
ns
Minimum RESET Assertion Duration2
OMR Bit 6 = 0
OMR Bit 6 = 1
2.
Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases:
After power-on reset
When recovering from Stop state
tRA
275,000T
128T
—
ns
RESET De-assertion to First External Address
Output
tRDA
33T
34T
ns
Edge-sensitive Interrupt Request Width
tIRW
1.5T
—
ns
IRQA, IRQB Assertion to External Data Memory
Access Out Valid, caused by first instruction
execution in the interrupt service routine
tIDM
15T
—
ns
IRQA, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the
interrupt service routine
tIG
16T
—
ns
IRQA Low to First Valid Interrupt Vector Address
Out recovery from Wait State3
3.
The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is not
the minimum required so that the IRQA interrupt is accepted.
tIRI
13T
—
ns
IRQA Width Assertion to Recover from Stop State4
4.
The interrupt instruction fetch is visible on the pins only in Mode 3.
5.
Parameters listed are guaranteed by design.
tIW
2T
—
ns
Delay from IRQA Assertion to Fetch of first
instruction (exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
tIF
—
275,000T
12T
ns
Duration for Level Sensitive IRQA Assertion to
Cause the Fetch of First IRQA Interrupt Instruction
(exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
tIRQ
—
275,000T
12T
ns
Delay from Level Sensitive IRQA Assertion to First
Interrupt Vector Address Out Valid (exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
tII
—
275,000T
12T
ns
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DSP56F801FA60E 制造商:Freescale Semiconductor 功能描述:Digital Signal Processor IC DSP Type:Pro
DSP56F801FA60E 制造商:Freescale Semiconductor 功能描述:DIGITAL SIGNAL PROCESSORLQFP3.6V
DSP56F801FA80 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 80Mhz/ 40MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
DSP56F801FA80E 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 16 BIT HYBRID CONTROLLER RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
DSP56F801FA80E 制造商:Freescale Semiconductor 功能描述:IC
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