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參數(shù)資料
| 型號： | DSP56F801FA80E |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | 16-bit Digital Signal Controllers |
| 中文描述： | 16位數(shù)字信號控制器 |
| 文件頁數(shù)： | 29/48頁 |
| 文件大?。?/td> | 375K |
| 代理商： | DSP56F801FA80E |
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Reset, Stop, Wait, Mode Select, and Interrupt Timing
56F801 Technical Data, Rev. 16
Freescale Semiconductor
29
3.6 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Table 3-11 Reset, Stop, Wait, Mode Select, and Interrupt Timing
1, 5
Operating Conditions:
V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.0–3.6 V, T
A
= –40
°
to +85
°
C, C
L
≤
50pF
1.
In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns.
Characteristic
Symbol
Min
Max
Unit
See
RESET Assertion to Address, Data and Control
Signals High Impedance
t
RAZ
—
21
ns
Figure 3-13
Minimum RESET Assertion Duration
2
OMR Bit 6 = 0
OMR Bit 6 = 1
2.
Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases:
After power-on reset
When recovering from Stop state
t
RA
275,000T
128T
—
—
ns
ns
Figure 3-13
RESET De-assertion to First External Address
Output
t
RDA
33T
34T
ns
Figure 3-13
Edge-sensitive Interrupt Request Width
t
IRW
1.5T
—
ns
Figure 3-14
IRQA, IRQB Assertion to External Data Memory
Access Out Valid, caused by first instruction
execution in the interrupt service routine
t
IDM
15T
—
ns
Figure 3-15
IRQA, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the
interrupt service routine
t
IG
16T
—
ns
Figure 3-15
IRQA Low to First Valid Interrupt Vector Address
Out recovery from Wait State
3
3.
the minimum required so that the IRQA interrupt is accepted.
The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is not
t
IRI
13T
—
ns
Figure 3-16
IRQA Width Assertion to Recover from Stop State
4
4.
The interrupt instruction fetch is visible on the pins only in Mode 3.
5.
Parameters listed are guaranteed by design.
t
IW
2T
—
ns
Figure 3-17
Delay from IRQA Assertion to Fetch of first
instruction (exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
t
IF
—
—
275,000T
12T
ns
ns
Figure 3-17
Duration for Level Sensitive IRQA Assertion to
Cause the Fetch of First IRQA Interrupt Instruction
(exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
t
IRQ
—
—
275,000T
12T
ns
ns
Figure 3-18
Delay from Level Sensitive IRQA Assertion to First
Interrupt Vector Address Out Valid (exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
t
II
—
—
275,000T
12T
ns
ns
Figure 3-18
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| DSP56F801 | 16-bit Hybrid Controller(16位混合控制器) |
| DSP56F803E | 16-bit Digital Signal Controllers |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSP56F801FA80E | 制造商:Freescale Semiconductor 功能描述:IC |
| DSP56F801PB | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:16-bit Digital Signal Processor |
| DSP56F802 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
| DSP56F802PB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:56F802 16-Bit Hybrid Controller Product Brief |
| DSP56F802TA60 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 60Mhz/30MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
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