參數(shù)資料
型號: DSP56F801FA80E
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: 16-bit Digital Signal Controllers
中文描述: 16位數(shù)字信號控制器
文件頁數(shù): 35/48頁
文件大小: 375K
代理商: DSP56F801FA80E
Quad Timer Timing
56F801 Technical Data, Rev. 16
Freescale Semiconductor
35
3.8 Quad Timer Timing
Figure 3-23 Timer Timing
3.9 Serial Communication Interface (SCI) Timing
Table 3-13 Timer Timing
1, 2
Operating Conditions:
V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.0–3.6 V, T
A
= –40
°
to +85
°
C, C
L
50pF
1.
In the formulas listed, T = clock cycle. For 80MHz operation, T = 12.5ns.
2.
Parameters listed are guaranteed by design.
Characteristic
Symbol
Min
Max
Unit
Timer input period
P
IN
4T+6
ns
Timer input high/low period
P
INHL
2T+3
ns
Timer output period
P
OUT
2T
ns
Timer output high/low period
P
OUTHL
1T
ns
Table 3-14 SCI Timing
4
Operating Conditions:
V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.0–3.6 V, T
A
= –40
°
to +85
°
C, C
L
50pF
Characteristic
Symbol
Min
Max
Unit
Baud Rate
1
1.
f
MAX
is the frequency of operation of the system clock in MHz.
The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.
BR
(f
MAX
*2.5)/(80)
Mbps
RXD
2
Pulse Width
2.
RXD
PW
0.965/BR
1.04/BR
ns
TXD
3
Pulse Width
3.
The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.
4.
Parameters listed are guaranteed by design.
TXD
PW
0.965/BR
1.04/BR
ns
Timer Inputs
Timer Outputs
P
OUTHL
P
OUTHL
P
OUT
P
IN
P
INHL
P
INHL
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