參數(shù)資料
型號(hào): DSP56F805E
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: 16-bit Digital Signal Controllers
中文描述: 16位數(shù)字信號(hào)控制器
文件頁(yè)數(shù): 33/56頁(yè)
文件大小: 415K
代理商: DSP56F805E
External Bus Asynchronous Timing
56F805 Technical Data, Rev. 15
Freescale Semiconductor
33
Figure 3-11 External Bus Asynchronous Timing
1.
T = Clock Period. For 80MHz operation, T = 12.5ns.
Timing is both wait state- and frequency-dependent. In the formulas listed, WS = the number of wait states and
2.
Parameters listed are guaranteed by design.
To calculate the required access time for an external memory for any frequency < 80Mhz, use this formula:
Top = Clock period @ desired operating frequency
WS = Number of wait states
Memory Access Time = (Top*WS) + (Top- 11.5)
A0–A15,
PS, DS
(See Note)
WR
D0–D15
RD
Note: During read-modify-write instructions and internal instructions, the address lines do not change state.
Data In
Data Out
t
AWR
t
ARDA
t
ARDD
t
RDA
t
RD
t
RDRD
t
RDWR
t
WRWR
t
WR
t
DOS
t
WRD
t
WRRD
t
AD
t
DOH
t
DRD
t
RDD
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