Port G
參數(shù)資料
型號(hào)： DSPB56374AFC
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 56/64頁(yè)
文件大?。?/td> 0K
描述： IC DSP 24BIT 150MHZ 80-LQFP
標(biāo)準(zhǔn)包裝： 90
系列： DSP56K/Symphony
類型： 音頻處理器
接口： 主機(jī)接口，I²C，SAI，SPI
時(shí)鐘速率： 150MHz
非易失內(nèi)存： ROM（84 kB）
芯片上RAM： 54kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.25V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 80-LQFP
供應(yīng)商設(shè)備封裝： 80-LQFP（14x14）
包裝： 托盤
DSP56374 Data Sheet, Rev. 4.2
Signal Groupings
Freescale Semiconductor
6
4.1
Power
4.2
Ground
Dedicated GPIO
Port G3
15
Timer
3
JTAG/OnCE Port
4
Note:
1 Pins are not 5 V. tolerant unless noted.
2 Port H signals are the GPIO port signals which are multiplexed with the MOD and HREQ signals.
3 Port G signals are the dedicated GPIO port signals.
4 Port C signals are the GPIO port signals which are multiplexed with the ESAI signals.
5 Port E signals are the GPIO port signals which are multiplexed with the ESAI_1 signals.
Table 4. Power Inputs
Power Name
Description
PLLA_VDD (1)
PLL Power— The voltage (3.3 V) should be well-regulated and the input should be provided with
an extremely low impedance path to the 3.3 VDD power rail. The user must provide adequate
external decoupling capacitors between PLLA_VDD and PLLA_GND. PLLA_VDD requires a filter
as shown in Figure 1 and Figure 2 below. See the DSP56374 technical data sheet for additional
details.
PLLP_VDD(1)
PLL Power— The voltage (3.3 V) should be well-regulated and the input should be provided with
an extremely low impedance path to the 3.3 VDD power rail. The user must provide adequate
external decoupling capacitors between PLLP_VDD and PLLP_GND.
PLLD_VDD (1)
PLL Power— The voltage (1.25 V) should be well-regulated and the input should be provided with
an extremely low impedance path to the 1.25 VDD power rail. The user must provide adequate
external decoupling capacitors between PLLD_VDD and PLLD_GND.
CORE_VDD (4)
Core Power—The voltage (1.25 V) should be well-regulated and the input should be provided with
an extremely low impedance path to the 1.25 VDD power rail. The user must provide adequate
external decoupling capacitors.
IO_VDD
(80-pin 4)
(52-pin 3)
SHI, ESAI, ESAI_1, WDT and Timer I/O Power —The voltage (3.3 V) should be well-regulated,
and the input should be provided with an extremely low impedance path to the 3.3 VDD power rail.
This is an isolated power for the SHI, ESAI, ESAI_1, WDT and Timer I/O. The user must provide
adequate external decoupling capacitors.
Table 5. Grounds
Ground Name
Description
PLLA_GND(1)
PLL Ground—The PLL ground should be provided with an extremely low-impedance path to
ground. This connection must be tied externally to all other chip ground connections. The user
must provide adequate external decoupling capacitors between PLLA_VDD and PLLA_GND.
Table 3. DSP56374 Functional Signal Groupings (continued)
Functional Group
Number of
Signals1
Detailed
Description
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