參數(shù)資料
型號(hào): DSPIC30F2010-20I/SO
廠商: Microchip Technology
文件頁(yè)數(shù): 45/66頁(yè)
文件大?。?/td> 0K
描述: IC DSPIC MCU/DSP 12K 28SOIC
產(chǎn)品培訓(xùn)模塊: dsPIC30F Quadrature Encoder Interface
Serial Communications using dsPIC30F I2C
Serial Communications using dsPIC30F SPI
Serial Communications using dsPIC30F UART
dsPIC30F 12 bit ADC - Part 2
dsPIC30F Addressing Modes - Part 1
dsPIC30F Architecture - Part 1
dsPIC30F DSP Engine & ALU
dsPIC30F Interrupts
dsPIC30F Motor Control PWM
dsPIC Timers
Asynchronous Stimulus
dsPIC30F Addressing Modes - Part 2
dsPIC30F Architecture - Part 2
dsPIC30F 12-bit ADC Part 1
標(biāo)準(zhǔn)包裝: 27
系列: dsPIC™ 30F
核心處理器: dsPIC
芯體尺寸: 16-位
速度: 20 MIPS
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 高級(jí)欠壓探測(cè)/復(fù)位,電機(jī)控制 PWM,QEI,POR,PWM,WDT
輸入/輸出數(shù): 20
程序存儲(chǔ)器容量: 12KB(4K x 24)
程序存儲(chǔ)器類(lèi)型: 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 2.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 6x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
包裝: 管件
配用: XLT28SO-1-ND - SOCKET TRANSITION 28SOIC 300MIL
其它名稱(chēng): DSPIC30F2010-20I/SOG
DSPIC30F201020IS
2010 Microchip Technology Inc.
DS70102K-page 5
dsPIC30F Flash Programming Specification
5.0
DEVICE PROGRAMMING
5.1
Overview of the Programming
Process
Once the programming executive has been verified
in memory (or loaded if not present), the dsPIC30F can
be programmed using the command set shown in
Table 5-1. A detailed description for each command is
TABLE 5-1:
COMMAND SET SUMMARY
Command
Description
SCHECK
Sanity check
READD
Read data EEPROM, Configuration
registers and device ID
READP
Read code memory
PROGD
Program one row of data EEPROM
and verify
PROGP
Program one row of code memory and
verify
PROGC
Program Configuration bits and verify
ERASEB
Bulk Erase, or erase by segment
ERASED
Erase data EEPROM
ERASEP
Erase code memory
QBLANK
Query if the code memory and data
EEPROM are blank
QVER
Query the software version
A high-level overview of the programming process is
illustrated in Figure 5-1. The process begins by enter-
ing Enhanced ICSP mode. The chip is then bulk
erased, which clears all memory to ‘1’ and allows the
device to be programmed. The Chip Erase is verified
before programming begins. Next, the code memory,
data Flash and Configuration bits are programmed. As
these memories are programmed, they are each
verified to ensure that programming was successful. If
no errors are detected, the programming is complete
and Enhanced ICSP mode is exited. If any of the
verifications fail, the procedure should be repeated,
starting from the Chip Erase.
If Advanced Security features are enabled, then
individual Segment Erase operations need to be
performed, based on user selections (i.e., based on the
specific needs of the user application). The specific
operations that are used typically depend on the order
in which various segments need to be programmed for
a given application or system.
describe the programming process in detail.
FIGURE 5-1:
PROGRAMMING FLOW
Start
Program and
Program and verify
Configuration bits
Finish
verify code
verify data
Enter Enhanced
Exit Enhanced ICSP
Mode
Perform Chip
Erase
Program
Configuration
registers to
ICSP mode
default value
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