參數(shù)資料
型號： DSPIC30F2010T-20E/MM
廠商： Microchip Technology
文件頁數(shù)： 6/49頁
文件大小： 0K
描述： IC DSPIC MCU/DSP 12K 28QFN
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
標(biāo)準(zhǔn)包裝： 1,600
系列： dsPIC™ 30F
核心處理器： dsPIC
芯體尺寸： 16-位
速度： 20 MIPS
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 高級欠壓探測/復(fù)位，電機(jī)控制 PWM，QEI，POR，PWM，WDT
輸入/輸出數(shù)： 20
程序存儲器容量： 12KB（4K x 24）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量： 512 x 8
電壓 - 電源 (Vcc/Vdd)： 2.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 6x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 28-VQFN 裸露焊盤
包裝： 帶卷 (TR)
dsPIC30F2010
DS70118J-page 14
2011 Microchip Technology Inc.
2.3
Divide Support
The dsPIC DSC devices feature a 16/16-bit signed
fractional divide operation, as well as 32/16-bit and 16/
16-bit signed and unsigned integer divide operations, in
the form of single instruction iterative divides. The
following instructions and data sizes are supported:
DIVF – 16/16 signed fractional divide
DIV.sd – 32/16 signed divide
DIV.ud – 32/16 unsigned divide
DIV.sw – 16/16 signed divide
DIV.uw – 16/16 unsigned divide
The 16/16 divides are similar to the 32/16 (same number
of iterations), but the dividend is either zero-extended or
sign-extended during the first iteration.
The divide instructions must be executed within a
REPEAT
loop. Any other form of execution (e.g., a
series of discrete divide instructions) will not function
correctly because the instruction flow depends on
RCOUNT. The divide instruction does not automatically
set up the RCOUNT value, and it must, therefore, be
explicitly and correctly specified in the REPEAT instruc-
tion, as shown in Table 2-2 (REPEAT will execute the
target instruction {operand value + 1} times). The
REPEAT
loop count must be set up for 18 iterations of
the DIV/DIVF instruction. Thus, a complete divide
operation requires 19 cycles.
2.4
DSP Engine
The DSP engine consists of a high-speed 17-bit x
17-bit multiplier, a barrel shifter, and a 40-bit adder/sub-
tracter (with two target accumulators, round and
saturation logic).
The DSP engine also has the capability to perform inher-
ent
accumulator-to-accumulator
operations,
which
require no additional data. These instructions are ADD,
SUB
, and NEG.
The DSP engine has various options selected through
various bits in the CPU Core Configuration Register
(CORCON), as listed below:
Fractional or integer DSP multiply (IF).
Signed or unsigned DSP multiply (US).
Conventional or convergent rounding (RND).
Automatic saturation on/off for ACCA (SATA).
Automatic saturation on/off for ACCB (SATB).
Automatic saturation on/off for writes to data
memory (SATDW).
Accumulator Saturation mode selection (ACC-
SAT).
A block diagram of the DSP engine is shown in
TABLE 2-2:
DIVIDE INSTRUCTIONS
Note:
The Divide flow is interruptible; however,
the user needs to save the context as
appropriate.
Note:
For CORCON layout, see Table 3-3.
TABLE 2-1:
DSP INSTRUCTION
SUMMARY
Instruction
Algebraic
Operation
ACC WB?
CLR
A = 0
Yes
ED
A = (x – y)2
No
EDAC
A = A + (x – y)2
No
MAC
A = A + (x y)
Yes
MAC
A = A + x2
No
MOVSAC
No change in A
Yes
MPY
A = x y
No
MPY.N
A = – x y
No
MSC
A = A – x y
Yes
Instruction
Function
DIVF
Signed fractional divide: Wm/Wn
→W0; Rem →W1
DIV.sd
Signed divide: (Wm + 1:Wm)/Wn
→W0; Rem →W1
DIV.ud
Unsigned divide: (Wm + 1:Wm)/Wn
→W0; Rem →W1
DIV.sw (
or DIV.s)
Signed divide: Wm/Wn
→W0; Rem →W1
DIV.uw (
or DIV.u)
Unsigned divide: Wm/Wn
→W0; Rem →W1
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