參數(shù)資料
型號(hào)： DSPIC30F2010T-20E/MM
廠商： Microchip Technology
文件頁數(shù)： 9/49頁
文件大?。?/td> 0K
描述： IC DSPIC MCU/DSP 12K 28QFN
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
標(biāo)準(zhǔn)包裝： 1,600
系列： dsPIC™ 30F
核心處理器： dsPIC
芯體尺寸： 16-位
速度： 20 MIPS
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 高級(jí)欠壓探測(cè)/復(fù)位，電機(jī)控制 PWM，QEI，POR，PWM，WDT
輸入/輸出數(shù)： 20
程序存儲(chǔ)器容量： 12KB（4K x 24）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量： 512 x 8
電壓 - 電源 (Vcc/Vdd)： 2.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 6x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 28-VQFN 裸露焊盤
包裝： 帶卷 (TR)
2011 Microchip Technology Inc.
DS70118J-page 17
dsPIC30F2010
The SA and SB bits are modified each time data passes
through the adder/subtracter, but can only be cleared by
the user. When set, they indicate that the accumulator
has overflowed its maximum range (bit 31 for 32-bit
saturation, or bit 39 for 40-bit saturation) and will be
saturated (if saturation is enabled). When saturation is
not enabled, SA and SB default to bit 39 overflow and
thus indicate that a catastrophic overflow has occurred.
If the COVTE bit in the INTCON1 register is set, SA and
SB bits will generate an arithmetic warning trap when
saturation is disabled.
The overflow and saturation status bits can optionally
be viewed in the Status Register (SR) as the logical OR
of OA and OB (in bit OAB), and the logical OR of SA
and SB (in bit SAB). This allows programmers to check
one bit in the STATUS register to determine if either
accumulator has overflowed, or one bit to determine if
either accumulator has saturated. This would be useful
for complex number arithmetic which typically uses
both the accumulators.
The device supports three Saturation and Overflow
modes.
1.
Bit 39 Overflow and Saturation:
When bit 39 overflow and saturation occurs, the
saturation logic loads the maximally positive 9.31
(0x7FFFFFFFFF) or maximally negative 9.31
value (0x8000000000) into the target accumula-
tor. The SA or SB bit is set and remains set until
cleared by the user. This is referred to as ‘super
saturation’ and provides protection against erro-
neous data or unexpected algorithm problems
(e.g., gain calculations).
2.
Bit 31 Overflow and Saturation:
When bit 31 overflow and saturation occurs, the
saturation logic then loads the maximally positive
1.31 value (0x007FFFFFFF) or maximally nega-
tive 1.31 value (0x0080000000) into the target
accumulator. The SA or SB bit is set and remains
set until cleared by the user. When this Saturation
mode is in effect, the guard bits are not used (so
the OA, OB or OAB bits are never set).
3.
Bit 39 Catastrophic Overflow
The bit 39 overflow status bit from the adder is
used to set the SA or SB bit, which remain set
until cleared by the user. No saturation operation
is performed and the accumulator is allowed to
overflow (destroying its sign). If the COVTE bit in
the INTCON1 register is set, a catastrophic
overflow can initiate a trap exception.
2.4.2.2
Accumulator ‘Write-Back’
The MAC class of instructions (with the exception of
MPY
, MPY.N, ED and EDAC) can optionally write a
rounded version of the high word (bits 31 through 16)
of the accumulator that is not targeted by the instruction
into data space memory. The write is performed across
the X bus into combined X and Y address space. The
following addressing modes are supported:
1.
W13, Register Direct:
The rounded contents of the non-target
accumulator are written into W13 as a 1.15
fraction.
2.
[W13]+=2, Register Indirect with Post-Increment:
The rounded contents of the non-target accumu-
lator are written into the address pointed to by
W13
as
a
1.15
fraction.
W13
is
then
incremented by 2 (for a word write).
2.4.2.3
Round Logic
The round logic is a combinational block, which
performs
a
conventional
(biased)
or
convergent
(unbiased) round function during an accumulator write
(store). The Round mode is determined by the state of
the RND bit in the CORCON register. It generates a 16-
bit, 1.15 data value which is passed to the data space
write saturation logic. If rounding is not indicated by the
instruction, a truncated 1.15 data value is stored and the
least significant word (lsw) is simply discarded.
Conventional rounding takes bit 15 of the accumulator,
zero-extends it and adds it to the ACCxH word (bits 16
through 31 of the accumulator). If the ACCxL word (bits
0 through 15 of the accumulator) is between 0x8000
and 0xFFFF (0x8000 included), ACCxH is incre-
mented. If ACCxL is between 0x0000 and 0x7FFF,
ACCxH is left unchanged. A consequence of this
algorithm is that over a succession of random rounding
operations, the value will tend to be biased slightly
positive.
Convergent (or unbiased) rounding operates in the
same manner as conventional rounding, except when
ACCxL equals 0x8000. If this is the case, the Least Sig-
nificant bit (bit 16 of the accumulator) of ACCxH is
examined. If it is ‘1’, ACCxH is incremented. If it is ‘0’,
ACCxH is not modified. Assuming that bit 16 is effec-
tively random in nature, this scheme will remove any
rounding bias that may accumulate.
The SAC and SAC.R instructions store either a trun-
cated (SAC) or rounded (SAC.R) version of the contents
of the target accumulator to data memory, via the X bus
(subject to data saturation, see Section 2.4.2.4 “Data
Space Write Saturation”). Note that for the MAC class
of instructions, the accumulator write-back operation
will function in the same manner, addressing combined
MCU (X and Y) data space though the X bus. For this
class of instructions, the data is always subject to
rounding.
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