參數(shù)資料
型號： DSPIC30F2020-30I/SP
廠商： Microchip Technology
文件頁數(shù)： 14/66頁
文件大?。?/td> 0K
描述： IC DSPIC MCU/DSP 12K 28DIP
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
標(biāo)準(zhǔn)包裝： 15
系列： dsPIC™ 30F
核心處理器： dsPIC
芯體尺寸： 16-位
速度： 30 MIP
連通性： I²C，IrDA，LIN，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 21
程序存儲器容量： 12KB（4K x 24）
程序存儲器類型： 閃存
RAM 容量： 512 x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-DIP（0.300"，7.62mm）
包裝： 管件
產(chǎn)品目錄頁面： 650 (CN2011-ZH PDF)
配用： DM300023-ND - KIT DEMO DSPICDEM SMPS BUCK
DV164005-ND - KIT ICD2 SIMPLE SUIT W/USB CABLE
2010 Microchip Technology Inc.
DS70102K-page 21
dsPIC30F Flash Programming Specification
6.6
Configuration Information in the
Hexadecimal File
To allow portability of code, the programmer must read
the
Configuration
register
locations
from
the
hexadecimal file. If configuration information is not
present in the hexadecimal file, a simple warning
message should be issued by the programmer.
Similarly, while saving a hexadecimal file, all
configuration information must be included. An option
to not include the configuration information can be
provided.
Microchip Technology Inc. feels strongly that this
feature is important for the benefit of the end customer.
6.7
Unit ID
The dsPIC30F devices contain 32 instructions of Unit
ID. These are located at addresses 0x8005C0 through
0x8005FF. The Unit ID can be used for storing product
information
such
as
serial
numbers,
system
manufacturing dates, manufacturing lot numbers and
other such application-specific information.
A Bulk Erase does not erase the Unit ID locations.
Instead, erase all executive memory using steps 1-4 as
shown in Table 12-1, and program the Unit ID along
with the programming executive. Alternately, use a
Row Erase to erase the row containing the Unit ID
locations.
6.8
Checksum Computation
Checksums for the dsPIC30F are 16 bits in size. The
checksum is to total sum of the following:
Contents of code memory locations
Contents of Configuration registers
Table A-1 describes how to calculate the checksum for
each device. All memory locations are summed one
byte at a time, using only their native data size. More
specifically, Configuration and device ID registers are
summed by adding the lower two bytes of these
locations (the upper byte is ignored), while code
memory is summed by adding all three bytes of code
memory.
Note:
The
checksum
calculation
differs
depending on the code-protect setting.
Table A-1 describes how to compute the
checksum for an unprotected device and
a read-protected device. Regardless of
the code-protect setting, the Configuration
registers can always be read.
7.0
PROGRAMMER –
PROGRAMMING EXECUTIVE
COMMUNICATION
7.1
Communication Overview
The programmer and programming executive have a
master-slave relationship, where the programmer is
the master programming device and the programming
executive is the slave.
All communication is initiated by the programmer in the
form of a command. Only one command at a time can
be sent to the programming executive. In turn, the
programming executive only sends one response to
the programmer after receiving and processing a
command. The programming executive command set
Commands”. The response set is described in
7.2
Communication Interface and
Protocol
The Enhanced ICSP interface is a 2-wire SPI interface
implemented using the PGC and PGD pins. The PGC
pin is used as a clock input pin, and the clock source
must be provided by the programmer. The PGD pin is
used for sending command data to, and receiving
response data from, the programming executive. All
serial data is transmitted on the falling edge of PGC
and latched on the rising edge of PGC. All data
transmissions are sent Most Significant bit (MSb) first,
using 16-bit mode (see Figure 7-1).
FIGURE 7-1:
PROGRAMMING
EXECUTIVE SERIAL
TIMING
Since a 2-wire SPI interface is used, and data transmis-
sions are bidirectional, a simple protocol is used to
control the direction of PGD. When the programmer
completes a command transmission, it releases the
PGD line and allows the programming executive to
drive this line high. The programming executive keeps
the PGD line high to indicate that it is processing the
command.
After the programming executive has processed the
command, it brings PGD low for 15
μsec to indicate to
the programmer that the response is available to be
PGC
PGD
12
3
11
13
15 16
14
12
LSb
14 13 12 11
45
6
MSb
1
2
3
...
4
5
P2
P3
P1
P1a
P1b
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