參數(shù)資料
型號： DSPIC30F2023-20E/PT
廠商： Microchip Technology
文件頁數(shù)： 38/66頁
文件大?。?/td> 0K
描述： IC DSPIC MCU/DSP 12K 44TQFP
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
特色產(chǎn)品： SMPS & Digital Power Conversion Solutions
標(biāo)準(zhǔn)包裝： 160
系列： dsPIC™ 30F
核心處理器： dsPIC
芯體尺寸： 16-位
速度： 20 MIPS
連通性： I²C，IrDA，LIN，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 35
程序存儲器容量： 12KB（4K x 24）
程序存儲器類型： 閃存
RAM 容量： 512 x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 12x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 44-TQFP
包裝： 托盤
產(chǎn)品目錄頁面： 650 (CN2011-ZH PDF)
配用： DV164005-ND - KIT ICD2 SIMPLE SUIT W/USB CABLE
2010 Microchip Technology Inc.
DS70102K-page 43
dsPIC30F Flash Programming Specification
11.7
Writing Configuration Memory
The FOSC, FWDT, FBORPOR and FICD registers are
not erasable. It is recommended that all Configuration
registers be set to a default value after erasing program
memory. The FWDT, FBORPOR and FICD registers
can be set to a default all ‘1’s value by programming
0xFFFF to each register. Since these registers contain
unimplemented bits that read as ‘0’ the default values
shown in Table 11-6 will be read instead of 0xFFFF.
The recommended default FOSC value is 0xC100,
which selects the FRC clock oscillator setting.
The FGS, FBS and FSS Configuration registers are
special since they enable code protection for the
device. For security purposes, once any bit in these
registers is programmed to ‘0’ (to enable some code
protection feature), it can only be set back to ‘1’ by
performing a Bulk Erase or Segment Erase as
described
in
these bits from a ‘0’ to ‘1’ is not possible, but they may
be programmed from a ‘1’ to a ‘0’ to enable code
protection.
Table 11-7 shows the ICSP programming details for
clearing the Configuration registers. In Step 1, the
Reset vector is exited. In Step 2, the write pointer (W7)
is loaded with 0x0000, which is the original destination
address (in TBLPAG 0xF8 of program memory). In
Step 3, the NVMCON is set to program one Configura-
tion register. In Step 4, the TBLPAG register is
initialized, to 0xF8, for writing to the Configuration
registers. In Step 5, the value to write to the each
Configuration register (0xFFFF) is loaded to W6. In
Step 6, the Configuration register data is written to the
write latch using the TBLWTL instruction. In Steps 7 and
8, the NVMCON is unlocked for programming and the
programming cycle is initiated, as described in
Mode”. In Step 9, the internal PC is set to 0x100 as a
safety measure to prevent the PC from incrementing
into unimplemented memory. Lastly, Steps 3-9 are
repeated six times until all seven Configuration
registers are cleared.
TABLE 11-6:
DEFAULT CONFIGURATION
REGISTER VALUES
Address
Register
Default Value
0xF80000
FOSC
0xC100
0xF80002
FWDT
0x803F
0xF80004
FBORPOR
0x87B3
0xF80006
FBS
0x310F
0xF80008
FSS
0x330F
0xF8000A
FGS
0x0007
0xF8000C
FICD
0xC003
TABLE 11-7:
SERIAL INSTRUCTION EXECUTION FOR WRITING CONFIGURATION
REGISTERS
Command
(Binary)
Data
(Hexadecimal)
Description
Step 1: Exit the Reset vector.
0000
040100
000000
GOTO 0x100
NOP
Step 2: Initialize the write pointer (W7) for the TBLWT instruction.
0000
200007
MOV
#0x0000, W7
Step 3: Set the NVMCON to program 1 Configuration register.
0000
24008A
883B0A
MOV
#0x4008, W10
MOV
W10, NVMCON
Step 4: Initialize the TBLPAG register.
0000
200F80
880190
MOV
#0xF8, W0
MOV
W0, TBLPAG
Step 5: Load the Configuration register data to W6.
0000
2xxxx0
000000
MOV
#<CONFIG_VALUE>, W0
NOP
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