參數(shù)資料
型號: DSPIC30F4013-20I/PT
廠商: Microchip Technology
文件頁數(shù): 102/153頁
文件大?。?/td> 0K
描述: IC DSPIC MCU/DSP 48K 44TQFP
產(chǎn)品培訓(xùn)模塊: Serial Communications using dsPIC30F CAN
Serial Communications using dsPIC30F I2C
Serial Communications using dsPIC30F SPI
Serial Communications using dsPIC30F UART
dsPIC30F 12 bit ADC - Part 2
dsPIC30F Addressing Modes - Part 1
dsPIC30F Architecture - Part 1
dsPIC30F DSP Engine & ALU
dsPIC30F Interrupts
dsPIC30F Motor Control PWM
dsPIC Timers
Asynchronous Stimulus
dsPIC30F Addressing Modes - Part 2
dsPIC30F Architecture - Part 2
dsPIC30F 12-bit ADC Part 1
標準包裝: 160
系列: dsPIC™ 30F
核心處理器: dsPIC
芯體尺寸: 16-位
速度: 20 MIPS
連通性: CAN,I²C,SPI,UART/USART
外圍設(shè)備: AC'97,欠壓檢測/復(fù)位,I²S,POR,PWM,WDT
輸入/輸出數(shù): 30
程序存儲器容量: 48KB(16K x 24)
程序存儲器類型: 閃存
EEPROM 大小: 1K x 8
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 2.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 13x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 托盤
配用: XLT44PT3-ND - SOCKET TRAN ICE 44MQFP/TQFP
AC164305-ND - MODULE SKT FOR PM3 44TQFP
其它名稱: DSPIC30F401320IPT
dsPIC30F3014/4013
DS70138G-page 52
2010 Microchip Technology Inc.
EXAMPLE 6-5:
DATA EEPROM BLOCK WRITE
6.4
Write Verify
Depending on the application, good programming
practice may dictate that the value written to the mem-
ory should be verified against the original value. This
should be used in applications where excessive writes
can stress bits near the specification limit.
6.5
Protection Against Spurious Write
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built-in. On power-up, the WREN bit is cleared;
also, the Power-up Timer prevents EEPROM write.
The write initiate sequence, and the WREN bit
together, help prevent an accidental write during
brown-out, power glitch or software malfunction.
MOV
#LOW_ADDR_WORD,W0
; Init pointer
MOV
#HIGH_ADDR_WORD,W1
MOV
W1,TBLPAG
MOV
#data1,W2
; Get 1st data
TBLWTL
W2,[ W0]++
; write data
MOV
#data2,W2
; Get 2nd data
TBLWTL
W2,[ W0]++
; write data
MOV
#data3,W2
; Get 3rd data
TBLWTL
W2,[ W0]++
; write data
MOV
#data4,W2
; Get 4th data
TBLWTL
W2,[ W0]++
; write data
MOV
#data5,W2
; Get 5th data
TBLWTL
W2,[ W0]++
; write data
MOV
#data6,W2
; Get 6th data
TBLWTL
W2,[ W0]++
; write data
MOV
#data7,W2
; Get 7th data
TBLWTL
W2,[ W0]++
; write data
MOV
#data8,W2
; Get 8th data
TBLWTL
W2,[ W0]++
; write data
MOV
#data9,W2
; Get 9th data
TBLWTL
W2,[ W0]++
; write data
MOV
#data10,W2
; Get 10th data
TBLWTL
W2,[ W0]++
; write data
MOV
#data11,W2
; Get 11th data
TBLWTL
W2,[ W0]++
; write data
MOV
#data12,W2
; Get 12th data
TBLWTL
W2,[ W0]++
; write data
MOV
#data13,W2
; Get 13th data
TBLWTL
W2,[ W0]++
; write data
MOV
#data14,W2
; Get 14th data
TBLWTL
W2,[ W0]++
; write data
MOV
#data15,W2
; Get 15th data
TBLWTL
W2,[ W0]++
; write data
MOV
#data16,W2
; Get 16th data
TBLWTL
W2,[ W0]++
; write data. The NVMADR captures last table access address.
MOV
#0x400A,W0
; Select data EEPROM for multi word op
MOV
W0,NVMCON
; Operate Key to allow program operation
DISI
#5
; Block all interrupts with priority <7 for
; next 5 instructions
MOV
#0x55,W0
MOV
W0,NVMKEY
; Write the 0x55 key
MOV
#0xAA,W1
MOV
W1,NVMKEY
; Write the 0xAA key
BSET
NVMCON,#WR
; Start write cycle
NOP
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