參數(shù)資料
型號(hào): DSPIC30F4013-20I/PT
廠商: Microchip Technology
文件頁數(shù): 59/153頁
文件大?。?/td> 0K
描述: IC DSPIC MCU/DSP 48K 44TQFP
產(chǎn)品培訓(xùn)模塊: Serial Communications using dsPIC30F CAN
Serial Communications using dsPIC30F I2C
Serial Communications using dsPIC30F SPI
Serial Communications using dsPIC30F UART
dsPIC30F 12 bit ADC - Part 2
dsPIC30F Addressing Modes - Part 1
dsPIC30F Architecture - Part 1
dsPIC30F DSP Engine & ALU
dsPIC30F Interrupts
dsPIC30F Motor Control PWM
dsPIC Timers
Asynchronous Stimulus
dsPIC30F Addressing Modes - Part 2
dsPIC30F Architecture - Part 2
dsPIC30F 12-bit ADC Part 1
標(biāo)準(zhǔn)包裝: 160
系列: dsPIC™ 30F
核心處理器: dsPIC
芯體尺寸: 16-位
速度: 20 MIPS
連通性: CAN,I²C,SPI,UART/USART
外圍設(shè)備: AC'97,欠壓檢測(cè)/復(fù)位,I²S,POR,PWM,WDT
輸入/輸出數(shù): 30
程序存儲(chǔ)器容量: 48KB(16K x 24)
程序存儲(chǔ)器類型: 閃存
EEPROM 大小: 1K x 8
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 2.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 13x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 托盤
配用: XLT44PT3-ND - SOCKET TRAN ICE 44MQFP/TQFP
AC164305-ND - MODULE SKT FOR PM3 44TQFP
其它名稱: DSPIC30F401320IPT
2010 Microchip Technology Inc.
DS70138G-page 151
dsPIC30F3014/4013
20.4
Reset
The
dsPIC30F3014/4013
differentiates
between
various kinds of Reset:
a)
Power-on Reset (POR)
b)
MCLR Reset during normal operation
c)
MCLR Reset during Sleep
d)
Watchdog Timer (WDT) Reset (during normal
operation)
e)
Programmable Brown-out Reset (BOR)
f)
RESET
Instruction
g)
Reset caused by trap lockup (TRAPR)
h)
Reset caused by illegal opcode or by using an
uninitialized W register as an Address Pointer
(IOPUWR)
Different registers are affected in different ways by var-
ious Reset conditions. Most registers are not affected
by a WDT wake-up since this is viewed as the resump-
tion of normal operation. Status bits from the RCON
register are set or cleared differently in different Reset
situations, as indicated in Table 20-5. These bits are
used in software to determine the nature of the Reset.
A block diagram of the On-Chip Reset Circuit is shown
A MCLR noise filter is provided in the MCLR Reset
path. The filter detects and ignores small pulses.
Internally generated Resets do not drive MCLR pin low.
FIGURE 20-2:
RESET SYSTEM BLOCK DIAGRAM
20.4.1
POR: POWER-ON RESET
A power-on event generates an internal POR pulse
when a VDD rise is detected. The Reset pulse occurs at
the POR circuit threshold voltage (VPOR) which is nom-
inally 1.85V. The device supply voltage characteristics
must meet specified starting voltage and rise rate
requirements. The POR pulse resets a POR timer and
places the device in the Reset state. The POR also
selects the device clock source identified by the
oscillator configuration fuses.
The POR circuit inserts a small delay, TPOR, which is
nominally 10
s and ensures that the device bias
circuits are stable. Furthermore, a user-selected
power-up time-out (TPWRT) is applied. The TPWRT
parameter is based on device Configuration bits and
can be 0 ms (no delay), 4 ms, 16 ms, or 64 ms. The
total delay is at device power-up, TPOR + TPWRT. When
these delays have expired, SYSRST is negated on the
next leading edge of the Q1 clock and the PC jumps to
the Reset vector.
The timing for the SYSRST signal is shown in
S
R
Q
MCLR
VDD
VDD Rise
Detect
POR
SYSRST
Sleep or Idle
Brown-out
Reset
BOREN
RESET
Instruction
WDT
Module
Digital
Glitch Filter
BOR
Trap Conflict
Illegal Opcode/
Uninitialized W Register
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