參數(shù)資料
型號: DSPIC30F4013-20I/PT
廠商: Microchip Technology
文件頁數(shù): 55/153頁
文件大小: 0K
描述: IC DSPIC MCU/DSP 48K 44TQFP
產(chǎn)品培訓(xùn)模塊: Serial Communications using dsPIC30F CAN
Serial Communications using dsPIC30F I2C
Serial Communications using dsPIC30F SPI
Serial Communications using dsPIC30F UART
dsPIC30F 12 bit ADC - Part 2
dsPIC30F Addressing Modes - Part 1
dsPIC30F Architecture - Part 1
dsPIC30F DSP Engine & ALU
dsPIC30F Interrupts
dsPIC30F Motor Control PWM
dsPIC Timers
Asynchronous Stimulus
dsPIC30F Addressing Modes - Part 2
dsPIC30F Architecture - Part 2
dsPIC30F 12-bit ADC Part 1
標(biāo)準(zhǔn)包裝: 160
系列: dsPIC™ 30F
核心處理器: dsPIC
芯體尺寸: 16-位
速度: 20 MIPS
連通性: CAN,I²C,SPI,UART/USART
外圍設(shè)備: AC'97,欠壓檢測/復(fù)位,I²S,POR,PWM,WDT
輸入/輸出數(shù): 30
程序存儲器容量: 48KB(16K x 24)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 2.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 13x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 托盤
配用: XLT44PT3-ND - SOCKET TRAN ICE 44MQFP/TQFP
AC164305-ND - MODULE SKT FOR PM3 44TQFP
其它名稱: DSPIC30F401320IPT
dsPIC30F3014/4013
DS70138G-page 148
2010 Microchip Technology Inc.
bit 5
LOCK: PLL Lock Status bit (read-only)
1
= Indicates that PLL is in lock
0
= Indicates that PLL is out of lock (or disabled)
Reset on POR or BOR. Reset when a valid clock switching sequence is initiated. Set when PLL lock
is achieved after a PLL start. Reset when lock is lost. Read zero when PLL is not selected as a system
clock
bit 4
Unimplemented: Read as ‘0’
bit 3
CF: Clock Fail Detect bit (read/clearable by application)
1
= FSCM has detected clock failure
0
= FSCM has NOT detected clock failure
Reset on POR or BOR. Reset when a valid clock switching sequence is initiated. Set when clock fail
detected
bit 2
Unimplemented: Read as ‘0’
bit 1
LPOSCEN: 32 kHz Secondary (LP) Oscillator Enable bit
1
= Secondary oscillator is enabled
0
= Secondary oscillator is disabled
Reset on POR or BOR.
bit 0
OSWEN: Oscillator Switch Enable bit
1
= Request oscillator switch to selection specified by NOSC<2:0> bits
0
= Oscillator switch is complete
Reset on POR or BOR. Reset after a successful clock switch. Reset after a redundant clock switch.
Reset after FSCM switches the oscillator to (Group 1) FRC.
REGISTER 20-1:
OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED)
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