參數(shù)資料
型號(hào): DSPIC30F5013-30I/PT
廠商: Microchip Technology
文件頁(yè)數(shù): 29/220頁(yè)
文件大小: 0K
描述: IC DSPIC MCU/DSP 66K 80TQFP
產(chǎn)品培訓(xùn)模塊: Serial Communications using dsPIC30F CAN
Serial Communications using dsPIC30F I2C
Serial Communications using dsPIC30F SPI
Serial Communications using dsPIC30F UART
dsPIC30F 12 bit ADC - Part 2
dsPIC30F Addressing Modes - Part 1
dsPIC30F Architecture - Part 1
dsPIC30F DSP Engine & ALU
Asynchronous Stimulus
dsPIC30F Addressing Modes - Part 2
dsPIC30F Architecture - Part 2
標(biāo)準(zhǔn)包裝: 119
系列: dsPIC™ 30F
核心處理器: dsPIC
芯體尺寸: 16-位
速度: 30 MIP
連通性: CAN,I²C,SPI,UART/USART
外圍設(shè)備: AC'97,欠壓檢測(cè)/復(fù)位,I²S,LVD,POR,PWM,WDT
輸入/輸出數(shù): 68
程序存儲(chǔ)器容量: 66KB(22K x 24)
程序存儲(chǔ)器類(lèi)型: 閃存
EEPROM 大小: 1K x 8
RAM 容量: 4K x 8
電壓 - 電源 (Vcc/Vdd): 2.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 80-TQFP
包裝: 托盤(pán)
產(chǎn)品目錄頁(yè)面: 651 (CN2011-ZH PDF)
配用: DM300024-ND - KIT DEMO DSPICDEM 1.1
XLT80PT3-ND - SOCKET TRAN ICE 80MQFP/TQFP
AC164320-ND - MODULE SKT MPLAB PM3 80TQFP
DM300004-2-ND - BOARD DEMO DSPICDEM.NET 2
DM300004-1-ND - BOARD DEMO DSPICDEM.NET 1
AC30F007-ND - MODULE SKT FOR DSPIC30F 80TQFP
DV164005-ND - KIT ICD2 SIMPLE SUIT W/USB CABLE
其它名稱(chēng): DSPIC30F501330IPT
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dsPIC30F5011/5013
DS70116J-page 124
2011 Microchip Technology Inc.
18.3.18
SLOT STATUS BITS
The SLOT<3:0> status bits in the DCISTAT SFR indi-
cate the current active time slot. These bits will corre-
spond to the value of the frame sync generator counter.
The user may poll these status bits in software when a
DCI interrupt occurs to determine what time slot data
was last received and which time slot data should be
loaded into the TXBUF registers.
18.3.19
CSDO MODE BIT
The CSDOM control bit controls the behavior of the
CSDO pin during unused transmit slots. A given trans-
mit time slot is unused if it’s corresponding TSEx bit in
the TSCON SFR is cleared.
If the CSDOM bit is cleared (default), the CSDO pin will
be low during unused time slot periods. This mode will
be used when there are only two devices attached to
the serial bus.
If the CSDOM bit is set, the CSDO pin will be tri-stated
during unused time slot periods. This mode allows mul-
tiple devices to share the same CSDO line in a multi-
channel application. Each device on the CSDO line is
configured so that it will only transmit data during
specific time slots. No two devices will transmit data
during the same time slot.
18.3.20
DIGITAL LOOPBACK MODE
Digital Loopback mode is enabled by setting the
DLOOP control bit in the DCICON1 SFR. When the
DLOOP bit is set, the module internally connects the
CSDO signal to CSDI. The actual data input on the
CSDI I/O pin will be ignored in Digital Loopback mode.
18.3.21
UNDERFLOW MODE CONTROL BIT
When an underflow occurs, one of two actions may
occur depending on the state of the Underflow mode
(UNFM) control bit in the DCICON1 SFR. If the UNFM
bit is cleared (default), the module will transmit ‘0’s on
the CSDO pin during the active time slot for the buffer
location. In this Operating mode, the codec device
attached to the DCI module will simply be fed digital
‘silence’. If the UNFM control bit is set, the module will
transmit the last data written to the buffer location. This
Operating mode permits the user to send continuous
data to the codec device without consuming CPU
overhead.
18.4
DCI Module Interrupts
The frequency of DCI module interrupts is dependent
on the BLEN<1:0> control bits in the DCICON2 SFR.
An interrupt to the CPU is generated each time the set
buffer length has been reached and a shadow register
transfer takes place. A shadow register transfer is
defined as the time when the previously written TXBUF
values are transferred to the transmit shadow registers
and new received values in the receive shadow
registers are transferred into the RXBUF registers.
18.5
DCI Module Operation During CPU
Sleep and Idle Modes
18.5.1
DCI MODULE OPERATION DURING
CPU SLEEP MODE
The DCI module has the ability to operate while in
Sleep mode and wake the CPU when the CSCK signal
is supplied by an external device (CSCKD = 1). The
DCI module will generate an asynchronous interrupt
when a DCI buffer transfer has completed and the CPU
is in Sleep mode.
18.5.2
DCI MODULE OPERATION DURING
CPU IDLE MODE
If the DCISIDL control bit is cleared (default), the mod-
ule will continue to operate normally even in Idle mode.
If the DCISIDL bit is set, the module will halt when Idle
mode is asserted.
18.6
AC-Link Mode Operation
The AC-Link protocol is a 256-bit frame with one 16-bit
data slot, followed by twelve 20-bit data slots. The DCI
module has two Operating modes for the AC-Link pro-
tocol. These Operating modes are selected by the
COFSM<1:0> control bits in the DCICON1 SFR. The
first AC-Link mode is called ‘16-bit AC-Link mode’ and
is selected by setting COFSM<1:0> = 10. The second
AC-Link mode is called ‘20-bit AC-Link mode’ and is
selected by setting COFSM<1:0> = 11.
18.6.1
16-BIT AC-LINK MODE
In the 16-bit AC-Link mode, data word lengths are
restricted to 16 bits. Note that this restriction only
affects the 20-bit data time slots of the AC-Link
protocol. For received time slots, the incoming data is
simply truncated to 16 bits. For outgoing time slots, the
4 LSbs of the data word are set to ‘0’ by the module.
This truncation of the time slots limits the A/D and DAC
data to 16 bits but permits proper data alignment in the
TXBUF and RXBUF registers. Each RXBUF and
TXBUF register will contain one data time slot value.
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