參數(shù)資料
型號: DSPIC33FJ32GP202T-I/SO
廠商: Microchip Technology
文件頁數(shù): 140/176頁
文件大?。?/td> 0K
描述: IC DSPIC MCU/DSP 32K 28SOIC
產(chǎn)品培訓模塊: Asynchronous Stimulus
標準包裝: 1,600
系列: dsPIC™ 33F
核心處理器: dsPIC
芯體尺寸: 16-位
速度: 40 MIP
連通性: I²C,IrDA,LIN,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數(shù): 21
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 10x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
包裝: 帶卷 (TR)
配用: DV164033-ND - KIT START EXPLORER 16 MPLAB ICD2
DM240001-ND - BOARD DEMO PIC24/DSPIC33/PIC32
其它名稱: DSPIC33FJ32GP202T-I/SOTR
dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
DS70290J-page 66
2007-2011 Microchip Technology Inc.
FIGURE 6-2:
SYSTEM RESET TIMING
Reset
Run
Device Status
VDD
VPOR
Vbor
VBOR
POR
BOR
SYSRST
TPWRT
TPOR
TBOR
Oscillator Clock
TOSCD
TOST
TLOCK
Time
FSCM
TFSCM
1
2
3
4
5
6
Note 1: POR: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is active
until VDD crosses the VPOR threshold and the delay TPOR has elapsed.
2: BOR: The on-chip voltage regulator has a BOR circuit that keeps the device in Reset until VDD crosses the
VBOR threshold and the delay TBOR has elapsed. The delay TBOR ensures the voltage regulator output
becomes stable.
3: PWRT Timer: The programmable power-up timer continues to hold the processor in Reset for a specific
period of time (TPWRT) after a BOR. The delay TPWRT ensures that the system power supplies have stabilized
at the appropriate level for full-speed operation. After the delay TPWRT has elapsed, the SYSRST becomes
inactive, which in turn enables the selected oscillator to start generating clock cycles.
4: Oscillator Delay: The total delay for the clock to be ready for various clock source selections are given in
5: When the oscillator clock is ready, the processor begins execution from location 0x000000. The user
application programs a GOTO instruction at the reset address, which redirects program execution to the
appropriate start-up routine.
6: The Fail-Safe Clock Monitor (FSCM), if enabled, begins to monitor the system clock when the system clock
is ready and the delay TFSCM elapsed.
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