參數(shù)資料
型號： DSPIC33FJ32GP202T-I/SO
廠商： Microchip Technology
文件頁數(shù)： 94/176頁
文件大?。?/td> 0K
描述： IC DSPIC MCU/DSP 32K 28SOIC
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
標(biāo)準(zhǔn)包裝： 1,600
系列： dsPIC™ 33F
核心處理器： dsPIC
芯體尺寸： 16-位
速度： 40 MIP
連通性： I²C，IrDA，LIN，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 21
程序存儲器容量： 32KB（32K x 8）
程序存儲器類型： 閃存
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 10x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
包裝： 帶卷 (TR)
配用： DV164033-ND - KIT START EXPLORER 16 MPLAB ICD2
DM240001-ND - BOARD DEMO PIC24/DSPIC33/PIC32
其它名稱： DSPIC33FJ32GP202T-I/SOTR
dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
DS70290J-page 24
2007-2011 Microchip Technology Inc.
3.6
Arithmetic Logic Unit (ALU)
The
dsPIC33FJ32GP202/204
and
dsPIC33FJ16GP304 ALU is 16 bits wide and is
capable of addition, subtraction, bit shifts and logic
operations. Unless otherwise mentioned, arithmetic
operations are 2’s complement in nature. Depending
on the operation, the ALU can affect the values of the
Carry (C), Zero (Z), Negative (N), Overflow (OV) and
Digit Carry (DC) Status bits in the SR register. The C
and DC Status bits operate as Borrow and Digit Borrow
bits, respectively, for subtraction operations.
The ALU can perform 8-bit or 16-bit operations,
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W
register array or data memory, depending on the
addressing mode of the instruction. Likewise, output
data from the ALU can be written to the W register array
or a data memory location.
The
dsPIC33FJ32GP202/204
and
dsPIC33FJ16GP304 CPU incorporates hardware
support for both multiplication and division. This
includes a dedicated hardware multiplier and support
hardware for 16-bit-divisor division.
Refer to the “dsPIC30F/33F Programmer’s Reference
Manual” (DS70157) for information on the SR bits
affected by each instruction.
3.6.1
MULTIPLIER
Using the high-speed 17-bit x 17-bit multiplier of the DSP
engine, the ALU supports unsigned, signed or mixed-sign
operation in several MCU multiplication modes:
16-bit x 16-bit signed
16-bit x 16-bit unsigned
16-bit signed x 5-bit (literal) unsigned
16-bit unsigned x 16-bit unsigned
16-bit unsigned x 5-bit (literal) unsigned
16-bit unsigned x 16-bit signed
8-bit unsigned x 8-bit unsigned
3.6.2
DIVIDER
The divide block supports 32-bit/16-bit and 16-bit/16-bit
signed and unsigned integer divide operations with the
following data sizes:
32-bit signed/16-bit signed divide
32-bit unsigned/16-bit unsigned divide
16-bit signed/16-bit signed divide
16-bit unsigned/16-bit unsigned divide
The quotient for all divide instructions ends up in W0
and the remainder in W1. 16-bit signed and unsigned
DIV instructions can specify any W register for both the
16-bit divisor (Wn) and any W register (aligned) pair
(W(m+1):Wm) for the 32-bit dividend. The divide
algorithm takes one cycle per bit of divisor, so both
32-bit/16-bit and 16-bit/16-bit instructions take the
same number of cycles to execute.
3.7
DSP Engine
The
DSP
engine
consists
of
a
high-speed
17-bit x 17-bit multiplier, a barrel shifter and a 40-bit
adder/subtracter (with two target accumulators, round
and saturation logic).
The dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
is a single-cycle instruction flow architecture; therefore,
concurrent operation of the DSP engine with MCU
instruction flow is not possible. However, some MCU
ALU and DSP engine resources can be used
concurrently by the same instruction (e.g., ED, EDAC).
The
DSP
engine
can
also
perform
accumulator-to-accumulator operations that require no
additional data. These instructions are ADD, SUB and
NEG.
The DSP engine has options selected through bits in
the CPU Core Control register (CORCON), as listed
below:
Fractional or integer DSP multiply (IF)
Signed or unsigned DSP multiply (US)
Conventional or convergent rounding (RND)
Automatic saturation on/off for AccA (SATA),
AccB (SATB) and writes to data memory
(SATDW)
Accumulator Saturation mode selection (ACC-
SAT)
A block diagram of the DSP engine is shown in
TABLE 3-1:
DSP INSTRUCTIONS
SUMMARY
Instruction
Algebraic
Operation
ACC Write
Back
CLR
A = 0
Yes
ED
A = (x - y)2
No
EDAC
A = A + (x - y)2
No
MAC
A = A + (x * y)
Yes
MAC
A = A + x2
No
MOVSAC
No change in A
Yes
MPY
A = x y
No
MPY
A = x2
No
MPY.N
A = - x y
No
MSC
A = A - x y
Yes
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